Intel E7-8891 v2 CM8063601377422 Benutzerhandbuch

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Integrated I/O (IIO) Configuration Registers
222
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.45 LNKCAP
PCI Express Link Capabilities
The Link Capabilities register identifies the PCI Express specific link capabilities. The 
link capabilities register needs some default values setup by the local host.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x9c
Bit
Attr
Default
Description
31:24
RW_O
0x0
port_number:
This field indicates the PCI Express port number for the link and is 
initialized by software/BIOS. IIO hardware does nothing with this bit.
23:23
RV
-
Reserved. 
22:22
RW_O
0x1
aspm_optionality_compliance:
21:21
RO_V
0x1
link_bandwidth_notification_capability:
A value of 1b indicates support for the Link Bandwidth Notification status 
and interrupt mechanisms.
Notes:
This bit will only be set if either “Report Speed Change” or “Report 
Configuration Change” bits are set in the DBG2STAT register bits 22 and 
20 respectively.
20:20
RO
0x1
data_link_layer_link_active_reporting_capable:
IIO supports reporting status of the data link layer so software knows 
when it can enumerate a device on the link or otherwise know the status 
of the link.
19:19
RO
0x1
surprise_down_error_reporting_capable:
IIO supports reporting a surprise down error condition
18:18
RO
0x0
clock_power_management:
Does not apply to processor
17:15
RW_O
0x2
l1_exit_latency:
This field indicates the L1 exit latency for the given PCI Express* port. It 
indicates the length of time this port requires to complete transition from 
L1 to L0.
000: Less than 1us
001: 1 us to less than 2 us
010: 2 us to less than 4 us
011: 4 us to less than 8 us
100: 8 us to less than 16 us
101: 16 us to less than 32 us
110: 32 us to 64 us
111: More than 64us
This register is made writable once by BIOS so that the value is settable 
based on experiments post-si.