Intel E7-8891 v2 CM8063601377422 Benutzerhandbuch

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Intel

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 Xeon

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Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

• PCI Configuration Registers (CSRs): CSRs are chipset specific registers that are 

located in PCI defined address space.

• Machine Specific Registers (MSRs): MSRs are machine specific registers that can be 

accessed by specific read and write instructions. MSRs are OS ring 0 and BIOS 
accessible.

• Memory-mapped I/O registers: These registers are mapped into the system 

memory map as MMIO low or MMIO high. They are accessed by any code, typically 
an OS driver running on the platform. This register space is introduced with the 
integration of some of the chipset functionality.

Configuration space registers are accessed via the well known configuration transaction 
mechanism defined in the PCI specification and this uses the bus:device:function 
number concept to address a specific device’s configuration space. If initiated by a 
remote CPU, accesses to PCI configuration registers are achieved via NcCfgRd/Wr 
transactions on Intel

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QPI.

All configuration register accesses are accessed over Message Channel through the 
UBox but might come from a variety of different sources: 

• Local  cores
• Remote cores (over Intel

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QuickPath Interconnect)

• PECI  or  JTAG

Configuration registers can be read or written in Byte, WORD (16-bit), or DWORD 
(32-bit) quantities. Accesses larger than a DWORD to PCI Express configuration space 
will result in unexpected behavior. All multibyte numeric fields use “little-endian” 
ordering (that is, lower addresses contain the least significant parts of the field).

In the tables shown for IIO devices (0 - 7), the PCI Bus numbers are all marked as “Bus 
0”. This means that the actual bus number is variable depending on which socket is 
used. The specific bus number for all PCIe* devices in Intel® Xeon® Processor E7-
2800/4800/8800 v2 Product Family is specified in the CPUBUSNO(0) which exists in the 
I/O module’s configuration space. Bus number is derived by the max bus range setting 
and processor socket number. 

In the tables shown for Uncore devices (8 - 19), the PCI Bus numbers are all marked as 
“bus 1”. This means that the actual bus number is CPUBUSNO(1), where CPUBUSNO(1) 
is programmable by BIOS depending on which socket is used. The specific bus number 
for all PCIe* devices in Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family 
is specified in the CPUBUSNO register. 

Each component in the processor is uniquely identified by a PCI bus address consisting 
of Bus Number, Device Number and Function Number. Device configuration is based on 
the PCI Type 0 configuration conventions. All processor registers appear on the PCI bus 
assigned for the processor socket. Bus number is derived by the max bus range setting 
and processor socket number.