Intel E7-8891 v2 CM8063601377422 Benutzerhandbuch
Produktcode
CM8063601377422
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
79
Datasheet Volume Two: Functional Description, February 2014
Registers Overview and Configuration Process
12.2.2
MSR Access
Machine Specific Registers are architectural and accessed by using specific
ReadMSR/WriteMSR instructions. MSRs are also accessible for Reads via PECI. MSRs
are always accessed as a naturally aligned 4- or 8-byte quantity.
ReadMSR/WriteMSR instructions. MSRs are also accessible for Reads via PECI. MSRs
are always accessed as a naturally aligned 4- or 8-byte quantity.
12.2.3
Memory-Mapped I/O Registers
The PCI standard provides not only configuration space registers but also registers
which reside in memory-mapped space. For PCI devices, this is typically where the
majority of driver programming occurs and the specific register definitions and
characteristics are provided by the device manufacturer. Access to these registers are
typically accomplished via CPU reads and writes to noncoherent (UC) or write-
combining (WC) space.
which reside in memory-mapped space. For PCI devices, this is typically where the
majority of driver programming occurs and the specific register definitions and
characteristics are provided by the device manufacturer. Access to these registers are
typically accomplished via CPU reads and writes to noncoherent (UC) or write-
combining (WC) space.
The Intel® Xeon® Processor E7-2800/4800/8800 v2 processor has relatively few of
these, however, the integration of some of the chipset functionality has brought with it
some I/O devices (e.g. the Intel® Quick Data DMA engine). These devices include
memory-mapped I/O registers.
these, however, the integration of some of the chipset functionality has brought with it
some I/O devices (e.g. the Intel® Quick Data DMA engine). These devices include
memory-mapped I/O registers.
Reads and writes to memory-mapped registers can be accomplished with 1, 2, 4, or 8
byte transactions.
byte transactions.
12.3
Register Terminology
The bits in configuration register descriptions will have an assigned attribute from the
following table. Bits without a Sticky attribute are set to their default value by a hard
reset.
following table. Bits without a Sticky attribute are set to their default value by a hard
reset.
Note:
The table below is a comprehensive list of all possible attributes and included for
completeness.
Table 12-3. Register attribute definitions (Sheet 1 of 2)
Attribute
Description
RO
Read Only: These bits can only be read by software, writes have no effect. The value of the bits
is determined by the hardware only.
RO_FW
Read Only Forced Write: These bits are read only from the perspective of the cores. However,
PCU microcode is able to write to these registers.
RO_V
Read Only - Variant: These bits are read-only by software but hardware can modify the value.
Typical example is a status register which is read-only.
Typical example is a status register which is read-only.
ROS_V
Read Only Sticky - Variant: These bits can only be read by software, writes have no effect.
Hardware can modify the value The value of the bits is determined by the hardware only. These
bits are only reinitialized to their default value by a PWRGOOD reset.
Hardware can modify the value The value of the bits is determined by the hardware only. These
bits are only reinitialized to their default value by a PWRGOOD reset.
WO
Write Only: These bits can only be written by microcode, reads return indeterminate values.
Microcode that wants to ensure this bit was written must read wherever the side-effect takes
place.
RW
Read / Write: These bits can be read and written by software.
RW_O
Read / Write Once: These bits can be read by software. After reset, these bits can only be
written by software once, after which the bits becomes ‘Read Only’.
RW_L
Read / Write Lock: These bits can be read and written by software. Hardware can make these
bits ‘Read Only’ via a separate configuration bit or other logic.