Intel J1850 FH8065301455200 Benutzerhandbuch
Produktcode
FH8065301455200
Serial ATA (SATA)
238
Datasheet
13.17.2
PCS_DWORD1 (pcs_dword1)—Offset 4h
Access Method
Default: 00600060h
11
0h
RW
reg_rcvdetect_pulse_width_ovrd: override enable for rcvdetect_pulse_width
10:8
0h
RW
reg_rcvdetect_pulse_width_2_0: override value for rcvdetect_pusle_width
7
1h
RW
reg_tx1_soft_reset_n: Active low reset to independently reset Tx lane1 in Display
Port 0: Lane 1 reset 1: Lane 1 active
6
0h
RW
reg_tx_8b10b_bypass: Bypass 8b10b encoder (for SAPIS etc interface.) 0 = Disable
8b/10b encoder bypass 1 = Enable 8b/10b encoder bypass
5
0h
RW
reg_tx_laneup: Unused in Tx
4
0h
RW
reg_left_txfifo_rst_master2: override enable = reg_lanedeskew_strap_ovrd
3
0h
RW
reg_right_txfifo_rst_master2: override enable = reg_lanedeskew_strap_ovrd
2
0h
RW
reg_plllinksynch_ovrden: Override enable for reg_plllinsync_ovrd 0 = Use default
delay in hardware 1 = Use reg_plllinksynch_ovrd
1
0h
RW
reg_plllinksynch_ovrd: override value for plllinksynch
0
0h
RW
reg_tx1_cmmdisparity: Sets the initial disparity during Compliance Measurement
Mode, used together with pcs_txcompliance pulse. 0 = set negative disparity 1 = set
positive disparity
Bit
Range
Default &
Access
Description
Type: Message Bus Register
(Size: 32 bits)
pcs_dword1: [Port: 0xA3] + (2200h + 4h)
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
reg_txfsm_4us_de
la
y_7_0
re
g_
so
ft
re
se
t_
en
ab
le
cri_rx
eb
_ei
o
se
nabl
e
cri_r
xdigfilts
q
_enabl
e
re
g_txfs
m
_
d
ela
y_o
vr
d
reg_txfsm_4us
_
de
la
y_11_8
re
g_pclk_r
ate
_1_0
reg_r
ate
_1_0
re
g_ph
ymode
_2_0
reg
_
mode
ov
re
n
re
g
_
da
ta
width
so
ft_r
es
et_n
re
g_d
igin
elb
en
re
g_d
igife
lbe
n
re
g_s
tr
apg
ro
u
p
_ovr
d
en
reg_y
ank_time
r_done_b_o
vr
d
re
g_y
ank_timer
_
don
e_b
_o
vrd_e
n