Acer Intel Celeron G530 KC.53001.CDG Benutzerhandbuch

Produktcode

KC.53001.CDG

Intel

Celeron

Processor on 0.13 Micron Process in the 478-Pin Package

Datasheet

Electrical Specifications

2.3.1

VCC Decoupling

Regulator solutions must provide bulk capacitance with a low Effective Series Resistance (ESR)
and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the
large current swings when the part is powering on or is entering or exiting low power states must
be provided by the voltage regulator solution (VR). For design guidelines, refer to

Table 1

for the

appropriate Platform Design Guide, and to the Intel

Pentium

4 Processor VR-Down Design

Guidelines.

2.3.2

System Bus AGTL+ Decoupling

The Celeron processor on 0.13 micron process integrates signal termination on the die and
incorporates high frequency decoupling capacitance on the processor package. Decoupling must
also be provided by the system motherboard for proper AGTL+ bus operation. For more
information, refer to the appropriate platform design guide listed in

Table 1

2.3.3

System Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly control the system bus interface speed as well as the core frequency of the
processor. As in previous generation processors, the Celeron processor on 0.13 micron process core
frequency is a multiple of the BCLK[1:0] frequency.

Like the Celeron processor in the 478-pin package, the Celeron processor on 0.13 micron process
uses a differential clocking implementation. For more information on clocking, refer to the CK408
Clock Design Guidelines and also the CK00 Clock Synthesizer/Driver Design Guidelines.