Acer Intel Celeron G530 KC.53001.CDG Benutzerhandbuch

28

 Datasheet

Routing topology recommendations can be found in the appropriate Platform Design Guide listed 
in 

. Termination resistors are not required for most AGTL+ signals because termination 

resistors are integrated into the processor silicon.

Valid high and low levels are determined by the input buffers which compare a signal’s voltage 
with a reference voltage called GTLREF (known as V

REF

 in previous documentation).

 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be 

generated on the system board using high precision voltage divider circuits. It is important that the 
system board impedance be held to the specified tolerance, and that the intrinsic trace capacitance 
for the AGTL+ signal group traces is known and is well-controlled. For more details on platform 
design, see the appropriate Platform Design Guide listed

 

in 

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

GTLREF

Bus Reference Voltage

2/3 VCC

 

– 2%

2/3 VCC

2/3 VCC

 

+ 2%

V

2,

 

3,

 

4

2.

The tolerances for this specification have been stated generically to enable the system designer to calculate
the minimum and maximum values across the range of VCC.

3.

GTLREF should be generated from VCC by a voltage divider of 1% tolerance resistors, or 1% tolerance
matched resistors. Refer to the appropriate Platform Design Guide listed in 

 for implementation details.

4.

The VCC referred to in these specifications is the instantaneous VCC.

R

TT

Termination Resistance

45

50

55

Ω

5

5.

R

TT

 is the on-die termination resistance measured at VOL of the AGTL+ output driver. Refer to processor 

I/O buffer models for I/V characteristics.

COMP[1:0]

COMP Resistance

50.49

51

51.51

Ω

6

6.

COMP resistance must be provided on the system board with 1% tolerance resistors. See the appropriate
Platform Design Guide for implementation details.