Acer Intel Celeron G530 KC.53001.CDG Benutzerhandbuch
Produktcode
KC.53001.CDG
Intel
®
Celeron
®
Processor on 0.13 Micron Process in the 478-Pin Package Datasheet
39
Electrical Specifications
Figure 19. FERR#/PBE# Valid Delay Timing
BCLK
STPCLK#
system bus
FERR#/PBE#
SG
Ack
FERR#
undefined
FERR#
Ta
PBE#
undefined
Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion)
Note: FERR# / PBE# is undefined from STPCLK# assertion until the stop grant acknowledge is driven on the processor system bus.
FERR# / PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined regions the PBE# signal
is driven. FERR# is driven at all other times.
is driven. FERR# is driven at all other times.
Figure 20. TAP Valid Delay Timing
V Valid
Signal
TCK
Th
Ts
Tx
Tx = T63 (Valid Time)
Ts = T61 (Setup Time)
Th = T62 (Hold Time)
V = 0.5 * Vcc
Ts = T61 (Setup Time)
Th = T62 (Hold Time)
V = 0.5 * Vcc
V