Acer Intel Celeron G530 KC.53001.CDG Benutzerhandbuch
Produktcode
KC.53001.CDG
Intel
®
Celeron
®
Processor on 0.13 Micron Process in the 478-Pin Package Datasheet
9
Introduction
Introduction
1
The Intel
®
Celeron
®
processor on 0.13 micron process and in the 478-pin package uses Flip-Chip
Pin Grid Array (FC-PGA2) package technology, and plugs into a 478-pin surface mount, Zero
Insertion Force (ZIF) socket, referred to as the mPGA478B socket. The Celeron processor on
0.13 micron process maintains the tradition of compatibility with IA-32 software. In this
document, the Celeron processor on 0.13 micron process may be referred to as the “Celeron
processor” or simply “the processor.”
Insertion Force (ZIF) socket, referred to as the mPGA478B socket. The Celeron processor on
0.13 micron process maintains the tradition of compatibility with IA-32 software. In this
document, the Celeron processor on 0.13 micron process may be referred to as the “Celeron
processor” or simply “the processor.”
The Celeron processor on 0.13 micron process is designed for uni-processor based Value PC
desktop systems. Features of the processor include hyper pipelined technology, a 400 MHz system
bus, and an execution trace cache. The 400 MHz system bus is a quad-pumped bus running off a
100 MHz system clock making 3.2 GB/s data transfer rates possible. The execution trace cache is a
first level cache that stores approximately 12k decoded micro-operations, which removes the
decoder from the main execution path.
desktop systems. Features of the processor include hyper pipelined technology, a 400 MHz system
bus, and an execution trace cache. The 400 MHz system bus is a quad-pumped bus running off a
100 MHz system clock making 3.2 GB/s data transfer rates possible. The execution trace cache is a
first level cache that stores approximately 12k decoded micro-operations, which removes the
decoder from the main execution path.
Additional features include advanced dynamic execution, advanced transfer cache, enhanced
floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The advanced
dynamic execution improves speculative execution and branch prediction internal to the processor.
The advanced transfer cache is a 128 KB, on-die level 2 (L2) cache. The floating point and multi-
media units have 128-bit wide registers with a separate register for data movement. SSE2 support
includes instructions for double-precision floating point, SIMD integer, and memory management.
Power management capabilities such as AutoHALT, Stop-Grant, and Sleep have been retained.
floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The advanced
dynamic execution improves speculative execution and branch prediction internal to the processor.
The advanced transfer cache is a 128 KB, on-die level 2 (L2) cache. The floating point and multi-
media units have 128-bit wide registers with a separate register for data movement. SSE2 support
includes instructions for double-precision floating point, SIMD integer, and memory management.
Power management capabilities such as AutoHALT, Stop-Grant, and Sleep have been retained.
The Celeron processor on 0.13 micron process 400 MHz system bus uses a split-transaction,
deferred reply protocol. This system bus is not compatible with the P6 processor family bus. The
400 MHz system bus uses Source-Synchronous Transfer (SST) of address and data to improve
throughput by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X).
Along with the 4X data bus, the address bus can deliver addresses two times per bus clock, and is
referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 3.2 GB/s.
deferred reply protocol. This system bus is not compatible with the P6 processor family bus. The
400 MHz system bus uses Source-Synchronous Transfer (SST) of address and data to improve
throughput by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X).
Along with the 4X data bus, the address bus can deliver addresses two times per bus clock, and is
referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 3.2 GB/s.
Intel will be enabling support components for the Celeron processor on 0.13 micron process
including a heatsink, heatsink retention mechanism, and socket. Manufacturability is a high
priority; hence, mechanical assembly can be completed from the top of the motherboard and should
not require any special tooling. The processor system bus uses a variant of GTL+ signalling
technology called Assisted Gunning Transceiver Logic (AGTL+) signalling technology.
including a heatsink, heatsink retention mechanism, and socket. Manufacturability is a high
priority; hence, mechanical assembly can be completed from the top of the motherboard and should
not require any special tooling. The processor system bus uses a variant of GTL+ signalling
technology called Assisted Gunning Transceiver Logic (AGTL+) signalling technology.
The processor includes an address bus powerdown capability which removes power from the
address and data pins when the system bus is not in use. This feature is always enabled on the
processor.
address and data pins when the system bus is not in use. This feature is always enabled on the
processor.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating that the signal is in the
active state when driven to a low level. For example, when RESET# is low, a reset has been
requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of
signals where the name does not imply an active state but describes part of a binary sequence
(such as address or data), the ‘#’ symbol implies that the signal is inverted. For example,
D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic
level, L= Low logic level).
active state when driven to a low level. For example, when RESET# is low, a reset has been
requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of
signals where the name does not imply an active state but describes part of a binary sequence
(such as address or data), the ‘#’ symbol implies that the signal is inverted. For example,
D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic
level, L= Low logic level).