Intel Xeon 5130 2.0GHz 124716 Datenbogen
Produktcode
124716
Dual-Core Intel
®
Xeon
®
Processor 5100 Series Datasheet
25
Electrical Specifications
Notes:
1.
Refer to
for signal descriptions.
2.
These signals may be driven simultaneously by multiple agents (Wired-OR).
outlines the signals which include on-die termination (R
TT
outlines
non AGTL+ signals including open drain signals.
voltages.
Note:
1.
Signals that have RTT in the package with 50 Ω pullup to V
TT
.
2.8
CMOS Asynchronous and Open Drain
Asynchronous Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize
CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,
and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain
signals are required to be asserted/deasserted for at least eight BCLKs in order for the
processor to recognize the proper signal state. See
CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,
and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain
signals are required to be asserted/deasserted for at least eight BCLKs in order for the
processor to recognize the proper signal state. See
for additional timing
requirements for entering and leaving the low power states.
2.9
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
Table 2-8.
AGTL+ Signal Description Table
AGTL+ signals with R
TT
AGTL+ signals with no R
TT
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#,
DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
REQ[4:0]#, RS[2:0]#, RSP#
BPM[5:0]#, RESET#
Table 2-9.
Non AGTL+ Signal Description Table
Signals with R
TT
Signals with no R
TT
FORCEPR#
1
, PROCHOT#
1
A20M#, BCLK[1:0], BSEL[2:0], FERR#/PBE#,
GTLREF_ADD, GTLREF_DATA, IERR#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, LL_ID[1:0], MS_ID[1:0], PECI,
PWRGOOD, SKTOCC#, SMI#, STPCLK#, TCK, TDI, TDO,
TESTHI[11:0], THERMTRIP#, TMS, TRDY#, TRST#,
VCC_DIE_SENSE, VCC_DIE_SENSE2, VID[6:1],
VID_SELECT, VSS_DIE_SENSE, VSS_DIE_SENSE2,
VTT_SEL
Table 2-10. Signal Reference Voltages
GTLREF
CMOS
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BPM[5:0]#, BPRI#, BR[1:0]#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,
DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#,
HITM#, LOCK#, MCERR#, RESET#, REQ[4:0]#,
RS[2:0]#, RSP#, TRDY#
A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#,
PWRGOOD, SMI#, STPCLK#, TCK, TDI, TMS, TRST#