Intel Xeon 5150 2.66 GHz 124695 Datenbogen
Produktcode
124695
Dual-Core Intel
®
Xeon
®
Processor 5100 Series Datasheet
71
Signal Definitions
Notes:
1.
For this processor land on the Dual-Core Intel
®
Xeon
®
Processor 5100 Series , the maximum number of symmetric agents is
one. Maximum number of priority agents is zero.
2.
For this processor land on the Dual-Core Intel
®
Xeon
®
Processor 5100 Series , the maximum number of symmetric agents is
two. Maximum number of priority agents is zero.
3.
For this processor land on the Dual-Core Intel
®
Xeon
®
Processor 5100 Series , the maximum number of symmetric agents is
two. Maximum number of priority agents is one.
§
TMS
I
TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
TRDY#
I
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a
write or implicit writeback data transfer. TRDY# must connect the appropriate pins of
all FSB agents.
TRST#
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low
during power on Reset.
V
CCPLL
I
The Dual-Core Intel
®
Xeon
®
Processor 5100 Series implements an on-die PLL filter
solution. The V
CCPLL
input is used as a PLL supply voltage.
VCC_DIE_SENSE
VCC_DIE_SENSE2
VCC_DIE_SENSE2
O
VCC_DIE_SENSE and VCC_DIE_SENSE2 provides an isolated, low impedance
connection to the processor core power and ground. This signal should be connected
to the voltage regulator feedback signal, which insures the output voltage (that is,
processor voltage) remains within specification. Please see the applicable platform
design guide for implementation details.
VID[6:1]
O
VID[6:1] (Voltage ID) pins are used to support automatic selection of power supply
voltages (V
CC
). These are CMOS signals that are driven by the processor and must be
pulled up through a resistor. Conversely, the voltage regulator output must be
disabled prior to the voltage supply for these pins becomes invalid. The VID pins are
needed to support processor voltage specification variations. See
for
definitions of these pins. The VR must supply the voltage that is requested by these
pins, or disable itself.
VID_SELECT
O
VID_SELECT is an output from the processor which selects the appropriate VID table
for the Voltage Regulator. This signal is not connected to the processor die. This signal
is a no-connect on the Dual-Core Intel
®
Xeon
®
Processor 5100 Series package.
VSS_DIE_SENSE
VSS_DIE_SENSE2
VSS_DIE_SENSE2
O
VSS_DIE_SENSE and VSS_DIE_SENSE2 provides an isolated, low impedance
connection to the processor core power and ground. This signal should be connected
to the voltage regulator feedback signal, which insures the output voltage (that is,
processor voltage) remains within specification. Please see the applicable platform
design guide for implementation details.
VTT
P
The FSB termination voltage input pins. Refer to
for further details.
VTT_OUT
O
The VTT_OUT signals are included in order to provide a local V
TT
for some signals that
require termination to V
TT
on the motherboard.
VTT_SEL
O
The VTT_SEL signal is used to select the correct V
TT
voltage level for the processor.
VTT_SEL is a no-connect on the Dual-Core Intel
®
Xeon
®
Processor 5100 Series
package.
Table 5-1.
Signal Definitions (Sheet 7 of 7)
Name
Type
Description
Notes