Hynix HMT351U7CFR8A-PBT0 Benutzerhandbuch

DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066s specified in table below. 

DDR3 SDRAM will also support corresponding tDS values (Table 43 and Table 50 in “DDR3L Device Opera-
tion”) as well as derating tables Table 46 in “DDR3L Device Operation” depending on Vih/Vil AC levels.

1. Vref = VrefDQ (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 29.
3. The ac peak noise on V

Ref

 may not allow V

Ref

 to deviate from V

RefDQ(DC)

 by more than +/-1% VDD (for reference: 

approx. +/- 13.5 mV). 4. For reference: approx. VDD/2 +/- 13.5 mV

4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 volt (table "Single Ended AC and DC Input Levels for Command and Address" on 

page 16) operation only. If the device is operated at 1.5V (table above), the respective levels in JESD79-3 (VIH/
L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) apply. The 1.5V levels (VIH/
L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) do not apply when the device is 
operated in the 1.35 voltage range.

VIH.DQ(DC90) DC input logic high

Vref + 0.09

VDD

Vref + 0.09

VDD

V

1

VIL.DQ(DC90) DC input logic low

VSS

Vref - 0.09

VSS

Vref - 0.09

V

1

VIH.DQ(AC160) AC input logic high

Vref + 0.160

Note2

-

-

V

1, 2, 5

VIL.DQ(AC160) AC input logic low

Note2

Vref - 0.160

-

-

V

1, 2, 5

VIH.DQ(AC135) AC Input logic high

Vref + 0.135

Note2

Vref + 0.135

Note2

V

1, 2, 5

VIL.DQ(AC135) AC input logic low

Note2

Vref - 0.135

Note2

Vref - 0.135

V

1, 2, 5

VIH.DQ(AC130) AC Input logic high

-

-

-

-

V

1, 2, 5

VIL.DQ(AC130) AC input logic low

-

-

-

-

V

1, 2, 5

V

RefDQ(DC

)

Reference Voltage 

for DQ, DM inputs

0.49 * VDD

0.51 * VDD

0.49 * VDD

0.51 * VDD

V

3, 4