Hynix HMT31GR7CFR4C-PBD8 Benutzerhandbuch
Rev. 1.1 / May. 2013
6
Input/Output Functional Descriptions
Symbol
Type
Polarity
Function
CK0
IN
Positive
Line
Positive line of the differential pair of system clock inputs that drives input to
the on-DIMM Clock Driver.
the on-DIMM Clock Driver.
CK0
IN
Negative
Line
Negative line of the differential pair of system clock inputs that drives the input
to the on-DIMM Clock Driver.
CK1
IN
Positive
Line
Terminated but not used on RDIMMs.
CK1
IN
Negative
Line
Terminated but not used on RDIMMs.
CKE[1:0]
IN
Active
High
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers of the SDRAMs. Taking CKE LOW pro-
vides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks
idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)
device input buffers and output drivers of the SDRAMs. Taking CKE LOW pro-
vides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks
idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)
S[3:0]
IN
Active
Low
Enables the command decoders for the associated rank of SDRAM when low
and disables decoders when high. When decoders are disabled, new com-
mands are ignored and previous operations continue. Other combinations of
these input signals perform unique functions, including disabling all outputs
(except CKE and ODT) of the register(s) on the DIMM or accessing internal
and disables decoders when high. When decoders are disabled, new com-
mands are ignored and previous operations continue. Other combinations of
these input signals perform unique functions, including disabling all outputs
(except CKE and ODT) of the register(s) on the DIMM or accessing internal
control words in the register device(s). For modules with two registers, S[3:2]
operate similarly to S[1:0] for the second set of register outputs or register
control words.
operate similarly to S[1:0] for the second set of register outputs or register
control words.
ODT[1:0]
IN
Active
High
On-Die Termination control signals
RAS, CAS, WE
IN
Active
Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE
define the operation to be executed by the SDRAM.
define the operation to be executed by the SDRAM.
V
REFDQ
Supply
Reference voltage for DQ0-DQ63 and CB0-CB7.
V
REFCA
Supply
Reference voltage for
A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1,
Par_In, ODT0 and ODT1.
BA[2:0]
IN
—
Selects which SDRAM bank
of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command
is being applied. Bank address also determines mode register is to be accessed
during an MRS cycle.
during an MRS cycle.
A[15:13,
12/BC,11,
10/AP,[9:0]
IN
—
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location out of
the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW)
or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by BA. A12 is also utilized for BL 4/8 identification for ‘’BL on the fly’’
the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW)
or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by BA. A12 is also utilized for BL 4/8 identification for ‘’BL on the fly’’
during CAS command. The address inputs also provide the op-code during
Mode Register Set commands.
Mode Register Set commands.
DQ[63:0],
CB[7:0]
I/O
—
Data and Check Bit Input/Output pins