Hynix HMT451U7AFR8C-PBT0 Benutzerhandbuch

A0–A15

SDRAM address bus

SCL

 I

2

C serial bus clock for EEPROM

BA0–BA2

SDRAM bank select

SDA

I

2

C serial bus data line for EEPROM

RAS

SDRAM row address strobe

SA0–SA2

I

2

C slave address select for EEPROM

CAS

SDRAM column address strobe

V

DD*

SDRAM core power supply

WE

SDRAM write enable

V

DD

Q

*

SDRAM I/O Driver power supply

S0–S1

DIMM Rank Select Lines

V

REF

DQ

SDRAM I/O reference supply

CKE0–CKE1

SDRAM clock enable lines

V

REF

CA

SDRAM command/address reference 

supply

ODT0–ODT1

On-die termination control lines

V

SS

Power supply return (ground)

DQ0–DQ63

DIMM memory data bus

V

DDSPD

Serial EEPROM positive power supply 

CB0–CB7

DIMM ECC check bits

NC

Spare pins (no connect)

DQS0–DQS8

SDRAM data strobes 
(positive line of differential pair)

TEST

Memory bus analysis tools
(unused on memory DIMMS)

DQS0–DQS8

SDRAM data strobes
(negative line of differential pair)

RESET

Set DRAMs to Known State

DM0–DM8

SDRAM data masks/high data strobes
 (x8-based x72 DIMMs)

V

TT

SDRAM I/O termination supply

CK0–CK1

SDRAM clocks 
(positive line of differential pair)

RSVD

Reserved for future use

CK0–CK1

SDRAM clocks 
(negative line of differential pair)

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