Intel E7-4870 v2 CM8063601272606 Benutzerhandbuch
Produktcode
CM8063601272606
Integrated I/O (IIO) Configuration Registers
196
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
8:8
RW
0x0
serre:
SERR Enable
For PCI Express/DMI ports, this field enables notifying the internal
For PCI Express/DMI ports, this field enables notifying the internal
core error logic of occurrence of an uncorrectable error (fatal or
nonfatal) at the port. The internal core error logic of the IIO module
then decides if/how to escalate the error further (pins/message, and
so forth). This bit also controls the propagation of PCI Express
ERR_FATAL and ERR_NONFATAL messages received from the port to
the internal IIO core error logic.
1: Fatal and Nonfatal error generation and Fatal and Nonfatal error
1: Fatal and Nonfatal error generation and Fatal and Nonfatal error
message forwarding is enabled
0: Fatal and Nonfatal error generation and Fatal and Nonfatal error
0: Fatal and Nonfatal error generation and Fatal and Nonfatal error
message forwarding is disabled
Refer to PCI Express Base Specification, Revision 2.0 for details of
Refer to PCI Express Base Specification, Revision 2.0 for details of
how this bit is used in conjunction with other control bits in the Root
Control register for forwarding errors detected on the PCI Express
interface to the system core error logic.
7:7
RO
0x0
idsel_stepping_wait_cycle_control:
IDSEL Stepping/Wait Cycle Control
Not applicable to internal IIO devices and is hardwired to 0.
Not applicable to internal IIO devices and is hardwired to 0.
6:6
RW
0x0
perre:
Parity Error Response
For PCI Express/DMI ports, the IIO module ignores this bit and
For PCI Express/DMI ports, the IIO module ignores this bit and
always does ECC/parity checking and signaling for data/address of
transactions both to and from IIO. This bit though affects the setting
of bit 8 in the PCISTS register.
5:5
RO
0x0
vga_palette_snoop_enable:
Not applicable to internal IIO device and is hardwired to 0.
4:4
RO
0x0
mwie:
Not applicable to internal IIO device and is hardwired to 0.
3:3
RO
0x0
sce:
Not applicable to PCI Express and is hardwired to 0.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x4
Bit
Attr
Default
Description