Fujifilm Xeon S26361-F3099-L828 Datenbogen
Produktcode
S26361-F3099-L828
14
Datasheet
2.2.3
Front Side Bus AGTL+ Decoupling
The Low Voltage Intel
®
Xeon™ processor with 800 MHz system bus integrates signal termination
on the die, as well as part of the required high frequency decoupling capacitance on the processor
package. However, additional high frequency capacitance must be added to the baseboard to
properly decouple the return currents from the front side bus. Bulk decoupling must also be
provided by the baseboard for proper AGTL+ bus operation.
package. However, additional high frequency capacitance must be added to the baseboard to
properly decouple the return currents from the front side bus. Bulk decoupling must also be
provided by the baseboard for proper AGTL+ bus operation.
2.3
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the
processor. As in previous processor generations, the Low Voltage Intel
processor. As in previous processor generations, the Low Voltage Intel
®
Xeon™ processor with
800 MHz system bus core frequency is a multiple of the BCLK[1:0] frequency. The processor bus
ratio multiplier will be set during manufacturing. The default setting will be the maximum speed
for the processor. It will be possible to override this setting using software. This will permit
operation at a speed lower than the processor’s tested frequency.
ratio multiplier will be set during manufacturing. The default setting will be the maximum speed
for the processor. It will be possible to override this setting using software. This will permit
operation at a speed lower than the processor’s tested frequency.
The BCLK[1:0] inputs directly control the operating speed of the front side bus interface. The
processor core frequency is configured during reset by using values stored internally during
manufacturing. The stored value sets the highest bus fraction at which the particular processor can
operate.
processor core frequency is configured during reset by using values stored internally during
manufacturing. The stored value sets the highest bus fraction at which the particular processor can
operate.
Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which
requires a constant frequency BCLK[1:0] input, with exceptions for spread spectrum clocking. The
Low Voltage Intel
requires a constant frequency BCLK[1:0] input, with exceptions for spread spectrum clocking. The
Low Voltage Intel
®
Xeon™ processor with 800 MHz system bus uses differential clocks. Details
regarding BCLK[1:0] driver specifications are provided in the CK409 Clock Synthesizer/Driver
Design Guidelines or CK409B Clock Synthesizer/Driver Design Guidelines.
Design Guidelines or CK409B Clock Synthesizer/Driver Design Guidelines.
contains core
frequency to front side bus multipliers and their corresponding core frequencies.
2.3.1
Front Side Bus Frequency Select Signals (BSEL[1:0])
Upon power up, the front side bus frequency is set to the maximum supported by the individual
processor. BSEL[1:0] are open-drain outputs, which must be pulled up to V
processor. BSEL[1:0] are open-drain outputs, which must be pulled up to V
TT
, and are used to
select the front side bus frequency. Please refer to
defines
the possible combinations of the signals and the frequency associated with each combination. The
frequency is determined by the processor(s), chipset, and clock synthesizer. All front side bus
agents must operate at the same core and front side bus frequencies. Individual processors will only
operate at their specified front side bus clock frequency.
frequency is determined by the processor(s), chipset, and clock synthesizer. All front side bus
agents must operate at the same core and front side bus frequencies. Individual processors will only
operate at their specified front side bus clock frequency.
Table 2.
Core Frequency to Front Side Bus Multiplier Configuration
Core Frequency to
Front Side Bus Multiplier
Core Frequency with
200 MHz Front Side Bus Clock
1/14
2.80 GHz