Intel Pentium 4 641 HH80552PG0882M Benutzerhandbuch

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Most processor FSB signals use Gunning Transceiver Logic (GTL+) signaling technology. 
Platforms implement a termination voltage level for GTL+ signals defined as V

TT

. V

TT

 must be 

provided via a separate voltage source and not be connected to V

CC

. This configuration allows for 

improved noise tolerance as processor frequency increases. Because of the speed improvements to 
the data and address bus, signal integrity and platform design methods have become more critical 
than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine 
if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board (see 

 for GTLREF specifications). Termination resistors are provided on the processor silicon 

and are terminated to V

TT

. Intel chipsets will also provide on-die termination, thus eliminating the 

need to terminate the bus on the system board for most GTL+ signals. 

Some GTL+ signals do not include on-die termination and must be terminated on the system board. 
See 

 for details regarding these signals.

The GTL+ bus depends on incident wave switching. Therefore, timing calculations for GTL+ 
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the 
FSB, including trace lengths, is highly recommended when designing a system.

For clean on-chip power distribution, the Pentium 4 processor in the 775-land package has 
226 V

CC

 (power), 24 V

TT

 and 273 V

SS

 

(ground) lands. All power lands must be connected to V

CC

, 

all V

TT

 lands must be connected to V

TT

, while all V

SS

 lands must be connected to a system ground 

plane. The processor V

CC

 lands must be supplied the voltage determined by the Voltage 

IDentification (VID) signals.

Due to its large number of transistors and high internal clock speeds, the processor is capable of 
generating large current swings between low and full power states. This may cause voltages on 
power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be 
taken in the board design to ensure that the voltage provided to the processor remains within the 
specifications listed in 

. Failure to do so can result in timing violations or reduced lifetime 

of the component. For further information and design guidelines, refer to the Voltage Regulator 
Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket.