STMicroelectronics M41T81SMY6F Linear IC M41T81SMY6F Datenbogen
Produktcode
M41T81SMY6F
M41T81S
Operation
Doc ID 10773 Rev 7
9/32
2 Operation
The M41T81S clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 20 bytes
contained in the device can then be accessed sequentially in the following order:
implementing a start condition followed by the correct slave address (D0h). The 20 bytes
contained in the device can then be accessed sequentially in the following order:
1. Tenths/hundredths of a second register
2. Seconds register
3. Minutes register
4. Century/hours register
5. Day register
6. Date register
7. Month register
8. Year register
9. Calibration register
10. Watchdog register
11 - 15. Alarm registers
16. Flags register
17 - 19. Reserved
20. Square wave register
The M41T81S clock continually monitors V
CC
for an out-of-tolerance condition. Should V
CC
fall below V
PFD
, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. Once V
from being written to the device from a an out-of-tolerance system. Once V
CC
falls below the
switchover voltage (V
SO
), the device automatically switches over to the battery and powers
down into an ultra-low current mode of operation to preserve battery life. If V
BAT
is less than
V
PFD
, the device power is switched from V
CC
to V
BAT
when V
CC
drops below V
BAT
. If V
BAT
is
greater than V
PFD
, the device power is switched from V
CC
to V
BAT
when V
CC
drops below
V
PFD
. Upon power-up, the device switches from battery to V
CC
at V
SO
. When V
CC
rises
above V
PFD
, it will recognize the inputs.
For more information on battery storage life refer to application note AN1012, "Predicting the
battery life and data retention period of NVRAMs and serial RTCs" .
battery life and data retention period of NVRAMs and serial RTCs" .
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.