Texas Instruments LM3431 Evaluation Board LM3431EVAL/NOPB LM3431EVAL/NOPB Datenbogen
Produktcode
LM3431EVAL/NOPB
SNVS547G – NOVEMBER 2007 – REVISED MAY 2013
If FETs are used, the
β
term can be ignored in both equations. The LED current in each string will be within
±Acc_single% of the set current. And the difference between any two strings will be within ±Acc_s-s% of each
other.
other.
PCB Layout
Good PCB layout is critical in all switching regulator designs. A poor layout can cause EMI problems, excess
switching noise, and improper device operation. The following key points should be followed to ensure a quality
layout.
switching noise, and improper device operation. The following key points should be followed to ensure a quality
layout.
Traces carrying large AC currents should be as wide and short as possible to minimize trace inductance and
associated noise spikes.
associated noise spikes.
These areas, shown hatched in
, are:
•
The connection between the output capacitor and diode
•
The PGND area between the output capacitor, R3 sense resistor, and bulk input capacitor
•
The switch node
The current sensing circuitry in current mode controllers can be easily affected by switching noise. Although the
LM3431 imposes 170ns of blanking time at the beginning of every cycle to ignore this noise, some may remain
after the blanking time. Following the important guidelines below will help minimize switching noise and its effect
on current sensing.
LM3431 imposes 170ns of blanking time at the beginning of every cycle to ignore this noise, some may remain
after the blanking time. Following the important guidelines below will help minimize switching noise and its effect
on current sensing.
As shown in
, ground the output capacitor as close as possible to the bottom of the sense resistor. This
connection should be somewhat isolated from the rest of the PGND plane (place no ground plane vias in this
area). The V
area). The V
OUT
side of the output capacitor should be placed close to the diode.
The SW node (the node connecting the diode anode, inductor, and FET drain) should be kept as small as
possible. This node is one of the main sources for radiated EMI. Sensitive traces should not be routed in the
area of the SW node or inductor.
possible. This node is one of the main sources for radiated EMI. Sensitive traces should not be routed in the
area of the SW node or inductor.
The CS pin is sensitive to noise. Be sure to route this trace away from the inductor and the switch node. The CS,
LG, and ILIM traces should be kept as short as possible. As shown below, R4 must be grounded close to the
ground side of R3.
LG, and ILIM traces should be kept as short as possible. As shown below, R4 must be grounded close to the
ground side of R3.
The VCC capacitor should be placed as close as possible to the IC and grounded close to the PGND pin. Take
care in routing any other VCC traces away from noise sources and use decoupling capacitors when using VCC
as an external voltage supply.
care in routing any other VCC traces away from noise sources and use decoupling capacitors when using VCC
as an external voltage supply.
A ceramic input capacitor must be connected as close as possible to the VIN pin and grounded close to the
PGND pin.
PGND pin.
An isolated ground area shown as SGND is recommended for small signal ground connections. The SGND
plane should connect to both the exposed pad (EP) and SGND pin. The SGND and PGND ground planes should
be connected to their respective pins and both pins should be connected only through the exposed pad, EP.
plane should connect to both the exposed pad (EP) and SGND pin. The SGND and PGND ground planes should
be connected to their respective pins and both pins should be connected only through the exposed pad, EP.
Components connecting all of the following pins should be placed close to the device and grounded to the SGND
plane: REF, REFIN, AFB, COMP, RT, FF, MODE/F, and SS/SH. These components and their traces should not
be routed near the switch node or inductor. The LED current sense resistors should be grounded to the SGND
plane for accurate current sensing. This area, shown as LGND in
plane: REF, REFIN, AFB, COMP, RT, FF, MODE/F, and SS/SH. These components and their traces should not
be routed near the switch node or inductor. The LED current sense resistors should be grounded to the SGND
plane for accurate current sensing. This area, shown as LGND in
, should be somewhat separated from
SGND and must provide enough copper area for the total LED current.
If driving more than 3 channels, the layout of the additional channels should be within a minimal area with short
trace lengths. This will help to reduce ringing and delay times. Connections to the LED array should be as short
as possible. Less than 25 cm is recommended. Longer lead lengths can cause excessive ringing or oscillation.
trace lengths. This will help to reduce ringing and delay times. Connections to the LED array should be as short
as possible. Less than 25 cm is recommended. Longer lead lengths can cause excessive ringing or oscillation.
A large, continuous ground plane should be placed as an inner or bottom layer for thermal dissipation. This plane
should be considered as a PGND area and not used for SGND connections. To optimize thermal performance,
multiple vias should be placed directly below the exposed pad to increase heat flow into the ground plane. The
recommended number of vias is 10-12 with a hole diameter between 0.20 mm and 0.33 mm. See TI Lit Number
should be considered as a PGND area and not used for SGND connections. To optimize thermal performance,
multiple vias should be placed directly below the exposed pad to increase heat flow into the ground plane. The
recommended number of vias is 10-12 with a hole diameter between 0.20 mm and 0.33 mm. See TI Lit Number
for more information.
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