Texas Instruments CDCLVD2102EVM - CDCLVD2102 Evaluation Module CDCLVD2102EVM CDCLVD2102EVM Datenbogen
Produktcode
CDCLVD2102EVM
Signal Path and Control Circuitry
www.ti.com
The evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLV\D1204
or CDCLVD2102. This fully assembled and factory-tested evaluation board allows complete validation of
device functionalities. For optimum performance, the board is equipped with SMA connectors and
well-controlled 50-
or CDCLVD2102. This fully assembled and factory-tested evaluation board allows complete validation of
device functionalities. For optimum performance, the board is equipped with SMA connectors and
well-controlled 50-
Ω
impedance microstrip transmission lines.
3
Signal Path and Control Circuitry
The CDCLVD1204/CDCLVD2102 support single-ended inputs up to 200 MHz and differential inputs up to
800 MHz. Each device provides up to four LVDS outputs operating at the input frequency or frequencies.
800 MHz. Each device provides up to four LVDS outputs operating at the input frequency or frequencies.
For more information, see the CDCLVD1204 (
) or CDCLVD2102 (
) product data sheet
for details.
4
Getting Started
The EVM has self-explanatory labeling and offers almost the same naming convention as used in the data
sheets. The labeling words appearing in bold italic type in this document duplicate the same spelling as
the actual labeling on the EVM board. The EVM can be used with single-ended or differential inputs.
sheets. The labeling words appearing in bold italic type in this document duplicate the same spelling as
the actual labeling on the EVM board. The EVM can be used with single-ended or differential inputs.
5
Device Selection
The same EVM is used for both CDCLVD1204 (2:4 single buffer) and CDCLVD2102 (1:2 dual buffer). The
selected box is highlighted in silkscreen for the particular device.
selected box is highlighted in silkscreen for the particular device.
6
Power Supply Connection
Connect the power supply source to the banana plug labeled VDD (P1) and connect the ground of the
power supply source to the GND (P2). The decoupling capacitors and ferrite bead isolate the EVM power
from the device’s power pins.
power supply source to the GND (P2). The decoupling capacitors and ferrite bead isolate the EVM power
from the device’s power pins.
Supply voltage of 2.375 V to 2.625 V can be used for this EVM.
7
Input Clock Selection
The CDCLVD1204/CDCLVD2102EVM offers options of receiving either a differential or a single-ended
clock as clock input. The default option is for the differential signal at both device inputs. The inputs can
be applied through the SMAs, J1, J2 and/or J3, J4. These inputs are ac coupled to the device inputs and
the common-mode voltage for these inputs after the ac-coupling capacitors are provided by 50
clock as clock input. The default option is for the differential signal at both device inputs. The inputs can
be applied through the SMAs, J1, J2 and/or J3, J4. These inputs are ac coupled to the device inputs and
the common-mode voltage for these inputs after the ac-coupling capacitors are provided by 50
Ω
(R3, R4
and R5, R6) to the device on-chip bias generator (V
AC_REF
) pins.
CDCLVD1204: Either of the two input clocks can be selected using the jumper JPM1. When Input 1 of
JPM1 is connected to GND, IN0 is selected. When Input 1 is connected to VDD, IN1 is selected.
JPM1 is connected to GND, IN0 is selected. When Input 1 is connected to VDD, IN1 is selected.
7.1
Configuring Single-Ended Input
For the single-ended clock applied to IN0, remove the capacitors C1 and C2, and replace them with 0-
Ω
resistors of the same footprint and also remove the biasing resistors R3 and R4. The single-ended
signal must be applied to INP0 (J2), and the DC bias voltage must be applied to INN0 (J1).
signal must be applied to INP0 (J2), and the DC bias voltage must be applied to INN0 (J1).
For the single-ended clock applied to IN1, remove the capacitors C3 and C4, replace them with 0-
Ω
resistors of the same footprint, and also remove the biasing resistors R5 and R6. The single-ended
signal must be applied to INP1 (J3), and the DC bias voltage must be applied to INN1 (J4).
signal must be applied to INP1 (J3), and the DC bias voltage must be applied to INN1 (J4).
8
Output Clock
The CDCLVD1204 generates up to four LVDS outputs, and two outputs are available on the EVM (OUT0
and OUT3) through the following SMAs: J5 and J6 for OUT0; J7 and J8 for OUT3. The LVDS outputs are
ac coupled to the respective SMAs. Each output pair has an option of 100-
and OUT3) through the following SMAs: J5 and J6 for OUT0; J7 and J8 for OUT3. The LVDS outputs are
ac coupled to the respective SMAs. Each output pair has an option of 100-
Ω
termination on the board (R7
and R8 – not populated).
Test points are available for OUT1 and OUT2 outputs.
CDCLVD2102: Using the control pin EN (labeled as Input 1), outputs can be disabled or enabled
2
Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board
SCAU043 – June 2010
Copyright © 2010, Texas Instruments Incorporated