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Texas Instruments BQ27505EVM - BQ27505 System-Side, Single-Cell Impedance Track??? Technology Evaluation Module BQ27505E BQ27505EVM Datenbogen

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BQ27505EVM
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Not Recommended for New Designs
SLUS884 – FEBRUARY 2009
www.ti.com
3.10
I
2
C-COMPATIBLE INTERFACE COMMUNICATION TIMING CHARACTERISTICS
T
A
= –40°C to 85°C, 2.4 V < V
CC
< 2.6 V; typical values at T
A
= 25°C and V
CC
= 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
r
SCL/SDA rise time
300
ns
t
f
SCL/SDA fall time
300
ns
t
w(H)
SCL pulse duration (high)
600
ns
t
w(L)
SCL pulse duration (low)
1.3
m
s
t
su(STA)
Setup for repeated start
600
ns
t
d(STA)
Start to first falling edge of SCL
600
ns
t
su(DAT)
Data setup time
100
ns
t
h(DAT)
Data hold time
0
ns
t
su(STOP)
Setup time for stop
600
ns
t
(BUF)
Bus free time between stop and start
66
m
s
f
SCL
Clock frequency
400
kHz
Figure 3-1. I
2
C-Compatible Interface Timing Diagrams
8
ELECTRICAL SPECIFICATIONS
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