Texas Instruments DEM-OPA-SO-2D Demonstration Fixture DEM-OPA-SO-2D DEM-OPA-SO-2D Datenbogen
Produktcode
DEM-OPA-SO-2D
www.ti.com
2
Circuit
R
4A
R
2A
R
3A
R
7A
Out A
DIS A
J
2A
GND
+V
P
1
2
3
5
4
11
14
1
C
3
R
8A
C
2
R
1A
IN A
J
1A
R
5A
R
6A
R
6B
+
L
2
L
1
C
1
+
R
4B
R
2B
R
3B
R
7B
6
8
7
R
1B
IN B
R
5B
C
6A
C
6B
C
4
C
5
J
3A
R
8B
J
3B
J
2B
J
1B
Out B
DIS B
S
-
V
S
3
Components
Circuit
The circuit schematic in
shows the connections for all possible components. Each configuration
uses only some of the components.
Figure 2. Schematic for DEM-OPA-SO-2D
Components that have RF performance similar to the ones listed in
may be substituted.
Table 1. Component Descriptions
PART
DESCRIPTION
C
1
, C
2
Tantalum Chip Capacitor, SMD EIA Size 3528, 20V
C
3
– C
6B
Multilayer Ceramic Chip Capacitor, SMD 1206, 50V
J
1A
– J
3B
SMA or SMB Board Jack (Amphenol 901-144-8)
L
1
, L
2
EMI-Suppression Ferrite Chip, SMD 1206 (Steward LI
1206 B 900 R)
1206 B 900 R)
P
1
Terminal Block, 3.5mm Centers (On-Shore Technology
ED555/3DS)
ED555/3DS)
R
1A
– R
8B
Metal Film Chip Resistor, SMD 1206, 1/8W
R
1
and R
7
set the I/O impedance; R
2
through R
6
set the gain; R
8
and C
6
set up the disable pin; and C
1
through C
5
are supply bypass capacitors. C
3
is optional; it adds a bypass between the supplies that
improves distortion performance for some models. L
1
and L
2
are ferrite chips that can reduce interactions
with the power supply at high frequencies. If not desired, they can be replaced with 0
Ω
resistors.
For single-supply operation, do not connect L
2
; otherwise, the –V
S
input to P
1
would be at ground
potential.
2
DEM-OPA-SO-2D Demonstration Fixture
SBOU002A – May 1998 – Revised May 2006