Microchip Technology IC MCU FLASH PIC16F874-20I/P DIP-40 MCP PIC16F874-20I/P Datenbogen

 1998-2013 Microchip Technology Inc.

DS30292D-page 15

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.

The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral features section.

00h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

01h

TMR0

Timer0 Module Register

xxxx xxxx

02h

PCL

Program Counter (PC) Least Significant Byte

0000 0000

03h

STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx

04h

FSR

Indirect Data Memory Address Pointer

xxxx xxxx

05h

PORTA

—

—

PORTA Data Latch when written: PORTA pins when read

--0x 0000

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

07h

PORTC

PORTC Data Latch when written: PORTC pins when read

xxxx xxxx

08h

PORTD

PORTD Data Latch when written: PORTD pins when read

xxxx xxxx

09h

PORTE

—

—

—

—

—

RE2

RE1

RE0

---- -xxx

0Ah

PCLATH

—

—

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

0Bh

INTCON

GIE PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0Ch

PIR1

PSPIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

0Dh

PIR2

—

—

EEIF

BCLIF

—

—

CCP2IF

-r-0 0--0

0Eh

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx

0Fh

TMR1H

Holding register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx

10h

T1CON

—

—

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

--00 0000

11h

TMR2

Timer2 Module Register

0000 0000

12h

T2CON

—

TOUTPS3

TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0 -000 0000

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx

70, 73

14h

SSPCON

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000 0000

15h

CCPR1L

Capture/Compare/PWM Register1 (LSB)

xxxx xxxx

16h

CCPR1H

Capture/Compare/PWM Register1 (MSB)

xxxx xxxx

17h

CCP1CON

—

—

CCP1X

CCP1Y

CCP1M3

CCP1M2

CCP1M1

CCP1M0

--00 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

19h

TXREG

USART Transmit Data Register

0000 0000

1Ah

RCREG

USART Receive Data Register

0000 0000

1Bh

CCPR2L

Capture/Compare/PWM Register2 (LSB)

xxxx xxxx

1Ch

CCPR2H

Capture/Compare/PWM Register2 (MSB)

xxxx xxxx

1Dh

CCP2CON

—

—

CCP2X

CCP2Y

CCP2M3

CCP2M2

CCP2M1

CCP2M0

--00 0000

1Eh

ADRESH

A/D Result Register High Byte

xxxx xxxx

1Fh

ADCON0

ADCS1

ADCS0

CHS2

CHS1

CHS0

GO/DONE

—

ADON

0000 00-0

Legend:

x

 = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. 

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose 

contents are transferred to the upper byte of the program counter.

2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.
5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.