Texas Instruments TPS65137A-366 Evaluation Board TPS65137AEVM-366 TPS65137AEVM-366 TPS65137AEVM-366 Datenbogen
Produktcode
TPS65137AEVM-366
IN
POS
V
η
D = 1
V
´
-
SLVS929A – MAY 2010 – REVISED OCTOBER 2012
Table 1. Programming Table for OUTN
BIT/RISING EDGES
OUTN (Vss)
DAC VALUE
BIT/RISING EDGES
OUTN(Vss)
DAC VALUE
Default
–4.93 V
00000
16
–3.7 V
10000
1
–5.23 V
00001
17
–3.62 V
10001
2
–5.13 V
00010
18
–3.52 V
10010
3
–5.03 V
00011
19
–3.42 V
10011
4
–4.93 V
00100
20
–3.32 V
10100
5
–4.83 V
00101
21
–3.22 V
10101
6
–4.73 V
00110
22
–3.12 V
10110
7
–4.63 V
00111
23
–3.02 V
10111
8
–4.53 V
01000
24
–2.92 V
11000
9
–4.43 V
01001
25
–2.82 V
11001
10
–4.33 V
01010
26
–2.72 V
11010
11
–4.23 V
01011
27
–2.62 V
11011
12
–4.13 V
01100
28
–2.52 V
11100
13
–4.03 V
01101
29
–2.42 V
11101
14
–3.93 V
01110
30
–2.31 V
11110
15
–3.82 V
01111
31
–2.21 V
11111
V
neg
Programming Transition Time t
set
for OUTN (C
T
)
The TPS65137 allows setting the transition time t
set
using an external capacitor connected to pin CT. The
transition time is the time period required to move OUTN from one voltage level to the next programmed voltage
level. When the CT pin is left open then the shortest possible transition time is programmed. When connecting a
capacitor to the CT pin then the transition time is given by the R-C time constant. This is given by the output
impedance of the CT pin of typically 250k
level. When the CT pin is left open then the shortest possible transition time is programmed. When connecting a
capacitor to the CT pin then the transition time is given by the R-C time constant. This is given by the output
impedance of the CT pin of typically 250k
Ω
and the external capacitance. Within one
τ
the output voltage OUTN
has reached 70% of its programmed value. An example is given when using 100nF for C
T
.
τ ≈
t
set70%
= 250 k
Ω
× C
T
= 250 k
Ω
× 100 nF = 25 mS
INPUT CAPACITOR SELECTION
The device typically requires a 4.7
μ
F ceramic input capacitor. Larger values can be used to lower the input
voltage ripple.
Table 2. Input Capacitor Selection
CAPACITOR
COMPONENT SUPPLIER
SIZE
4.7
μ
F/10 V
Taiyo Yuden LMK107BJ475
0603
10
μ
F/10 V
Taiyo Yuden LMK212BJ106
0805
10
μ
F/6.3 V
Taiyo Yuden JMK107BJ106
0603
BOOST CONVERTER DESIGN CONSIDERATION, V
pos
The positive output consists of a boost converter using a LDO as post regulator. The maximum output current is
limited by the minimum current limit of the LDO, of 200mA. The component values and output current are
calculated at maximum load current in continuous conduction operation. The typical switching frequency during
this operation mode is 1.4MHz.
limited by the minimum current limit of the LDO, of 200mA. The component values and output current are
calculated at maximum load current in continuous conduction operation. The typical switching frequency during
this operation mode is 1.4MHz.
The boost converter duty cycle is:
(1)
To calculate the duty cycle, a good estimation for the efficiency,
η
, is 75% or it can be taken out of the typical
curve in Figure 1. In order to calculate the maximum output current of the boost converter for a certain input
voltage, the following formula is used:
voltage, the following formula is used:
12
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: