Texas Instruments TPS61181(82/81A)-259 Evaluation Board TPS61181(82/81A)EVM-259 TPS61181AEVM-259 TPS61181AEVM-259 Datenbogen
Produktcode
TPS61181AEVM-259
C2
1 µF
10 WLED in series, 120 mA total
C2a
1 µF
L1
10 µH
D1
IFB1
IFB2
IFB3
IFB4
IFB5
IFB6
IFB2
IFB3
IFB4
IFB5
IFB6
V
O
SW
Fault
V
BAT
Cin
EN
DCTRL
ISET
PGND
GND
R1
62 KW
TPS61181A
C4
0.1 µF
4.5 V to 24 V
C1a
2.2 µF
EN
PWM Dimming
R2
51W
51W
C3
1 µF
C1
2.2 µF
C1, C1a: Murata GRM 219R61E225K
C2, C2a: Murata GRM 21BR71H105K
C3: Murata GRM 21BR71H105K
C4: Murata GRM 185R61A105K
C2, C2a: Murata GRM 21BR71H105K
C3: Murata GRM 21BR71H105K
C4: Murata GRM 185R61A105K
L1: TOKO A 915AY -100 M
D1: VISHAY SS 2P5-E3/84A
D1: VISHAY SS 2P5-E3/84A
SLVSAN6A
–
FEBRUARY 2011
–
REVISED MARCH 2011
isolation MOSFET. During a short circuit condition, the catch diode (D2 in typical application circuit) is forward
biased when the isolation FET is turned off. The drain of the isolation FET swings below ground. The voltage
across the isolation FET can be momentarily greater than the input voltage. Therefore, select a 30V MOSFET for
a 24V maximum input. The on resistance of the FET has a large impact on power conversion efficiency since the
FET carries the input voltage. Select a MOSFET with R
biased when the isolation FET is turned off. The drain of the isolation FET swings below ground. The voltage
across the isolation FET can be momentarily greater than the input voltage. Therefore, select a 30V MOSFET for
a 24V maximum input. The on resistance of the FET has a large impact on power conversion efficiency since the
FET carries the input voltage. Select a MOSFET with R
ds(on)
less than 100m
Ω
to limit the power losses.
LAYOUT CONSIDERATION
As for all switching power supplies, especially those providing high current and using high switching frequencies,
layout is an important design step. If layout is not carefully done, the regulator could show instability as well as
EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor, C3 in the typical
application circuit, needs not only to be close to the V
layout is an important design step. If layout is not carefully done, the regulator could show instability as well as
EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor, C3 in the typical
application circuit, needs not only to be close to the V
BAT
pin, but also to the GND pin in order to reduce the input
ripple seen by the IC. The input capacitor, C1 in the typical application circuit, should be placed close to the
inductor. The SW pin carries high current with fast rising and falling edges. Therefore, the connection between
the pin to the inductor and Schottky should be kept as short and wide as possible. It is also beneficial to have the
ground of the output capacitor C2 close to the PGND pin since there is large ground return current flowing
between them. When laying out signal ground, it is recommended to use short traces separated from power
ground traces, and connect them together at a single point, for example on the thermal pad.
inductor. The SW pin carries high current with fast rising and falling edges. Therefore, the connection between
the pin to the inductor and Schottky should be kept as short and wide as possible. It is also beneficial to have the
ground of the output capacitor C2 close to the PGND pin since there is large ground return current flowing
between them. When laying out signal ground, it is recommended to use short traces separated from power
ground traces, and connect them together at a single point, for example on the thermal pad.
Thermal pad needs to be soldered on to the PCB and connected to the GND pin of the IC. Additional thermal via
can significantly improve power dissipation of the IC.
can significantly improve power dissipation of the IC.
ADDITIONAL APPLICATION CIRCUITS
Figure 15. Audible Noise Reduction Circuit
16
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©
2011, Texas Instruments Incorporated
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