Texas Instruments CDCLVD1213EVM - CDCLVD1213 Evaluation Module CDCLVD1213EVM CDCLVD1213EVM Datenbogen
Produktcode
CDCLVD1213EVM
Getting Started
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The evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVD1213.
This fully assembled and factory-tested evaluation board allows complete validation of device
functionalities. For optimum performance, the board is equipped with SMA connectors and well-controlled
50-
This fully assembled and factory-tested evaluation board allows complete validation of device
functionalities. For optimum performance, the board is equipped with SMA connectors and well-controlled
50-
Ω
impedance microstrip transmission lines.
1.2
Signal Path and Control Circuitry
The CDCLVD1213 supports differential input up to 800 MHz. Each device provides up to three LVDS
outputs operating at the input frequency and one output with divide by /1, /2, or /4 frequency.
outputs operating at the input frequency and one output with divide by /1, /2, or /4 frequency.
For more information, see the CDCLVD1213 product data sheet (
) for details.
2
Getting Started
The EVM has self-explanatory labeling and offers almost the same naming convention as used in the data
sheet. All words appearing in bold italic print in this document are the actual labeling on the EVM.
sheet. All words appearing in bold italic print in this document are the actual labeling on the EVM.
3
Power Supply Connection
Connect the power supply source to the banana plug labeled VDD2.5V (P3), and connect the ground of
the power supply source to the GND (P2). Place the jumpers between 2 and 3 for JP6 and JP7. Ensure
that LED D2 and D3 are on.
the power supply source to the GND (P2). Place the jumpers between 2 and 3 for JP6 and JP7. Ensure
that LED D2 and D3 are on.
Decoupling capacitors and ferrite beads isolate the EVM power from the device’s power pins. Supply
voltage of a 2.375-V to 2.625-V range can be used in this EVM.
voltage of a 2.375-V to 2.625-V range can be used in this EVM.
The EVM has an option of providing 3.3 V (P1) and an LDO to convert 3.3 V to 2.5 V. The LDO (U3) is
unpopulated on the EVM.
unpopulated on the EVM.
4
Input Clock Connection
The inputs can be applied through the SMAs, J2 and J3. These inputs are ac coupled to the device inputs
and the common-mode voltage for these inputs after the ac-coupling capacitors are provided externally by
R7 (0
and the common-mode voltage for these inputs after the ac-coupling capacitors are provided externally by
R7 (0
Ω
) and R2 and R4.
The device input has an internal 140-
Ω
resistor. So, for 50-
Ω
characteristics impedance lines, an external
350
Ω
is populated at R9.
5
Output Clock
The CDCLVD1213 generates up to four LVDS outputs. Four outputs are available on the EVM through the
following SMAs: J5 and J6 for QP0; J7 and J8 for QP1; J9 and J10 for QP2; and J11 and J12 for QD.
The LVDS outputs are ac coupled to the respective SMAs. Each output pair has an option of 100-
following SMAs: J5 and J6 for QP0; J7 and J8 for QP1; J9 and J10 for QP2; and J11 and J12 for QD.
The LVDS outputs are ac coupled to the respective SMAs. Each output pair has an option of 100-
Ω
termination on the board (R23 - R26 – unpopulated).
Table 1. Divider Selection Table for QD Output
DIV (JP1)
Divider Ratio
0 (GND)
/1
OPEN
/2
1 (VDD2.5VMISC)
/4
6
Onboard Oscillator/VCO
This EVM has an option of oscillator or VCO whose output is directly connected to the inputs of the
CDCLVD12313 through R1 and R3. The oscillator (U2) and the associated components are unpopulated
on the EVM.
CDCLVD12313 through R1 and R3. The oscillator (U2) and the associated components are unpopulated
on the EVM.
7
The EVM Board Schematic
through
show the printed-circuit board (PCB) schematics.
2
Low-Additive Jitter, Four-LVDS-Outputs Clock Buffer With Divider EVM
SCAU044 – July 2010
Copyright © 2010, Texas Instruments Incorporated