Texas Instruments TLV70018EVM-503 Evaluation Module TLV70018EVM-503 TLV70018EVM-503 Datenbogen
Produktcode
TLV70018EVM-503
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Board Layout
5
Board Layout
This section provides the TLV700xxEVM-503 board layout and illustrations
5.1
Layout
When laying out the board for the TLV700xx, TI recommends that the board be designed with separate
ground planes for Vin and Vout which are only connected at the GND pin of the device. Also, the ground
connection for the bypass capacitor must be connected directly to the GND pin of the device. By following
the foregoing two guidelines, you can improve the PSRR performance of the TLV700xx. See the
TLV700xx data sheet for specific layout guidelines.
ground planes for Vin and Vout which are only connected at the GND pin of the device. Also, the ground
connection for the bypass capacitor must be connected directly to the GND pin of the device. By following
the foregoing two guidelines, you can improve the PSRR performance of the TLV700xx. See the
TLV700xx data sheet for specific layout guidelines.
Figure 1. Assembly Layer
5
SLUU391 – December 2009
TLV700xxEVM-503
Copyright © 2009, Texas Instruments Incorporated