Texas Instruments THS5661A Evaluation Module THS5661EVM THS5661EVM Datenbogen
Produktcode
THS5661EVM
List of Figures
1-1.
THS56X1 EVM Block Diagram
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1-2.
Mating of Connectors on the THS56X1 EVM to the Tektronix HFS9009 Pattern Generator
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1-3.
Mating of Connectors on the THS56X1 EVM to the SMA
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Ribbon Cable Adapter
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1-4.
Mating of Connectors on the C542DSK to the C542 DSKplus
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1-5.
Connecting the THS56X1A Outputs to J8 and J9
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2-1.
PWB Layers
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2-2.
Board Layout, Layer 1
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2-3.
Board Layout, Layer 2
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2-4.
Board Layout, Layer 3
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2-5.
Board Layout, Layer 4
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2-6.
Silk Screen
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3-1.
EVM Schematic Diagram
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3-2.
Reconfiguration Hardware Location
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3-3.
Direct Connect Jumper Configuration for THS56X1A
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3-4.
Jumper Configuration for Internal Reference Voltage
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3-5.
Jumper Configuration for External Reference
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3-6.
External Clock Signal
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List of Tables
1-1.
Package Styles Available
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1-2.
General ADC Features
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1-3.
Possible DACs
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3-1.
Jumper Functions
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3-2.
Analog Voltage Supply Configuration Options
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3-3.
Digital Input Options
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3-4.
Shipping Condition of Jumpers W1 Through W9
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3-5.
Jumper Configuration for Internal Reference
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3-6.
Jumper Configuration for External VREF
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3-7.
Connector Pin and Function Assignments
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3-8.
J4 and J2 Power Connectors
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3-9.
J6, J7, J8, and J9 Analog Output Signal Connectors
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3-10.
C542/C54xxDSK/Microprocessor Control Connector
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3-11.
J1 Parallel Data Connector
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3-12.
Function of Connector J5
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3
SLAU032C
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February 2001
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Revised April 2011
List of Figures
Copyright
©
2001
–
2011, Texas Instruments Incorporated