Texas Instruments BUF08630EVM - BUF08630 Evaluation Module BUF08630EVM BUF08630EVM Datenbogen
Produktcode
BUF08630EVM
BUF08630EVM Hardware Overview
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3.7.5
JMP4: I
2
C SCK Control Setting
Jumper JMP4 selects where the BUF08630 I
2
C SCL pin is connected. If JMP4 is set in the INT position,
the I
2
C clock signal is generated from the I2C_SCK_ISO signal from the USB_DIG_Platform.
When JMP4 is set in the EXT position, an external source connected to SCL pin of terminal T2 can be
used to provide the I
used to provide the I
2
C SCK signal for the BUF08630.
3.7.6
JMP5: I
2
C SDA Control Setting
Jumper JMP5 selects where the BUF08630 I
2
C SDA pin is connected. If JMP5 is set in the INT position,
the I
2
C data signal is generated from the I2C_SDA_ISO signal from the USB_DIG_Platform.
When JMP5 is set in the EXT position, an external source connected to SDA pin of terminal T2 can be
used to provide the I
used to provide the I
2
C SDA signal for the BUF08630.
3.7.7
JMP6: V
COM
Supply Control Setting
Jumper JMP6 selects where the BUF08630 V
COM
supply pin is connected. If JMP6 is set to the SHORT
position, the V
COM
supply pin is connected to the V
S
pin.
When JMP6 is set in the OPEN position, an external supply connected to terminal T6 can be used to
provide the V
provide the V
COM
supply voltage for the BUF08630.
3.7.8
BUF08630 Device Placement
The BUF08630_Test_Board allows the user two separate locations on the board where the BUF08630
test device can be installed. The U1 location on the BUF08630_Test_Board allows for a BUF08630 device
that is soldered down on a DIP adaptor board to be installed on the BUF08630_Test_Board. The output
capability of the BUF08630 that is soldered on this adaptor board can be fully evaluated. The PowerPAD
of this soldered BUF08630 is connected correctly, and allows the device to dissipate the necessary power
while being evaluated.
test device can be installed. The U1 location on the BUF08630_Test_Board allows for a BUF08630 device
that is soldered down on a DIP adaptor board to be installed on the BUF08630_Test_Board. The output
capability of the BUF08630 that is soldered on this adaptor board can be fully evaluated. The PowerPAD
of this soldered BUF08630 is connected correctly, and allows the device to dissipate the necessary power
while being evaluated.
The U2 location on the BUF08630_Test_Board is a 20-pin QFN/MLF test socket that allows the user to
evaluate and program many devices very quickly. One drawback to this socket is that there is no
connection to the PowerPAD of the BUF08630. Because of this drawback, while in this socket, the
BUF08630 cannot operate ar ts full output capability as a result of thermal dissipation limitations..
evaluate and program many devices very quickly. One drawback to this socket is that there is no
connection to the PowerPAD of the BUF08630. Because of this drawback, while in this socket, the
BUF08630 cannot operate ar ts full output capability as a result of thermal dissipation limitations..
CAUTION
Only one location should be populated at a time. The use of both locations
simultaneously will likely damage one or both of the devices being tested.
simultaneously will likely damage one or both of the devices being tested.
3.7.9
Terminal Strip TPG2
Terminal strip TPG2 provides the individual channel output signals on a single row of headers as well as a
row of vias. This footprint provides the user with multiple options on how to interface the output signals of
the BUF08630 with their display panel. The user can also develop a custom cable to connect directly to
the headers to thedesired panels or to solder directly to the individual vias.
row of vias. This footprint provides the user with multiple options on how to interface the output signals of
the BUF08630 with their display panel. The user can also develop a custom cable to connect directly to
the headers to thedesired panels or to solder directly to the individual vias.
14
BUF08630EVM User Guide and Software Tutorial
SBOU091 – September 2010
Copyright © 2010, Texas Instruments Incorporated