Texas Instruments Evaluation Board for the LM25066I LM25066I-EVM/NOPB LM25066I-EVM/NOPB Datenbogen
Produktcode
LM25066I-EVM/NOPB
t
ON
= -(R
L
x C
L
) x In
(I
LIM
x R
L
) - V
SYS
(I
LIM
x R
L
)
t
ON
=
V
SYS
x C
L
I
LIM
V
SENSE
= I
L
x R
S
=
R
PWR
1.71 x 10
5
x V
DS
R
S
x P
FET(LIM)
V
DS
=
SNVS824C – JUNE 2012 – REVISED MARCH 2013
POWER LIMIT THRESHOLD
The LM25066I/A determines the power dissipation in the external MOSFET (Q
1
) by monitoring the drain current
(the current in R
S
), and the V
DS
of Q
1
(SENSE to OUT pins). The resistor at the PWR pin (R
PWR
) sets the
maximum power dissipation for Q
1
and is calculated from
R
PWR
= 1.71 x 10
5
x R
S
x P
MOSFET(LIM)
(2)
where P
MOSFET(LIM)
is the desired power limit threshold for Q
1
and R
S
is the current sense resistor described in
. For example, if R
S
is 10 m
Ω
and the desired power limit threshold is 20W, R
PWR
calculates to 34.2
k
Ω
. If Q
1
’s power dissipation reaches the threshold, Q
1
’s gate is controlled to regulate the load current, keeping
Q
1
’s power from exceeding the threshold. For proper operation of the power limiting feature, R
PWR
must be
≤
150
k
Ω
. While the power limiting circuit is active, the fault timer is active as described in
Typically, power limit is reached during startup, or if the output voltage falls because of a severe overload or
short circuit. The programmed maximum power dissipation should have a reasonable margin from the maximum
power defined by the SOA chart, especially if retry is enabled since the MOSFET will be repeatedly stressed
during fault restart cycles. The MOSFET manufacturer should be consulted for guidelines. If the application does
not require use of the power limit function, the PWR pin can be left open. The accuracy of the power limit
function at turn-on may degrade if a very low value power dissipation limit is set. The reason for this caution is
that the voltage across the sense resistor, which is monitored and regulated by the power limit circuit, is lowest at
turn-on when the regulated current is at a minimum. The voltage across the sense resistor during power limit can
be expressed as follows:
short circuit. The programmed maximum power dissipation should have a reasonable margin from the maximum
power defined by the SOA chart, especially if retry is enabled since the MOSFET will be repeatedly stressed
during fault restart cycles. The MOSFET manufacturer should be consulted for guidelines. If the application does
not require use of the power limit function, the PWR pin can be left open. The accuracy of the power limit
function at turn-on may degrade if a very low value power dissipation limit is set. The reason for this caution is
that the voltage across the sense resistor, which is monitored and regulated by the power limit circuit, is lowest at
turn-on when the regulated current is at a minimum. The voltage across the sense resistor during power limit can
be expressed as follows:
(3)
where I
L
is the current in R
S
and V
DS
is the voltage across Q
1
. For example, if the power limit is set at 20W with
R
S
= 10 m
Ω
and V
DS
= 15V, the sense resistor voltage calculates to 13.3 mV, which is comfortably regulated by
the LM25066I/A. However, if the power limit is set lower (e.g. 2W), the sense resistor voltage calculates to 1.33
mV. At this low level, noise and offsets within the LM25066I/A may degrade the power limit accuracy. To
maintain accuracy, the sense resistor voltage should not be less than 5 mV.
mV. At this low level, noise and offsets within the LM25066I/A may degrade the power limit accuracy. To
maintain accuracy, the sense resistor voltage should not be less than 5 mV.
TURN-ON TIME
The output turn-on time depends on whether the LM25066I/A operates in current limit, or in both power limit and
current limit, during turn-on.
current limit, during turn-on.
A) Turn-on with current limit only: The current limit threshold (I
LIM
) is determined by the current sense resistor
(R
S
). If the current limit threshold is less than the current defined by the power limit threshold at maximum V
DS
,
the circuit operates at the current limit threshold only during turn-on. Referring to
A, as the load current
reaches I
LIM
, the gate-to-source voltage is controlled at V
GSL
to maintain the current at I
LIM
. As the output voltage
reaches its final value (V
DS
≊
0V) the drain current reduces to its normal operating value. The time for the OUT
pin voltage to transition from zero volts to V
SYS
is equal to:
(4)
where C
L
is the load capacitance. For example, if V
SYS
= 12V, C
L
= 1000 µF, and I
LIM
= 1A, t
ON
calculates to 12
ms. The maximum instantaneous power dissipated in the MOSFET is 12W. This calculation assumes the time
from t
from t
1
to t
2
in
(a) is small compared to t
ON
and the load does not draw any current until after the output
voltage has reached its final value, and PGD switches high (
A). The Fault Timeout Period must be set
longer than t
ON
to prevent a fault shutdown before the turn-on sequence is complete.
If the load draws current during the turn-on sequence (
B), the turn-on time is longer than the above
calculation and is approximately equal to:
(5)
where R
L
is the load resistance. The Fault Timeout Period must be set longer than t
ON
to prevent a fault
shutdown before the turn-on sequence is complete.
Copyright © 2012–2013, Texas Instruments Incorporated
23
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