Texas Instruments Evaluation Board for the LM25066I LM25066I-EVM/NOPB LM25066I-EVM/NOPB Datenbogen
Produktcode
LM25066I-EVM/NOPB
Alert Mask D8h
From PMBus
From other
fault inputs
fault inputs
ARA Auto Mask
Set
Clear
Fault Condition
ARA Operation Flag Succeeded
CLEAR_FAULT Command Received
SMBA
SNVS824C – JUNE 2012 – REVISED MARCH 2013
Table 48. SMBus Timing Definition (continued)
Symbol
Parameter
Limits
Unit
Comments
Min
Max
T
LOW:SEXT
Cumulative clock low extend time (slave device)
25
ms
(3)
T
LOW:MEXT
Cumulative low extend time (master device)
10
ms
(4)
T
F
Clock or Data Fall Time
20
300
ns
(5)
T
R
Clock or Data Rise Time
20
300
ns
(5)
(3)
T
LOW:SEXT
is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If
a slave exceeds this time, it is expected to release both its clock and data lines and reset itself.
(4)
T
LOW:MEXT
is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from
start-to-ack, ack-to-ack, or ack-to-stop.
(5)
Rise and fall time is defined as follows:•
T
R
= ( V
ILMAX
– 0.15) to (V
IHMIN
+ 0.15)•
T
F
= 0.9 VDD to (V
ILMAX
– 0.15)
SMBA Response
The SMBA effectively has two masks:
1. The Alert Mask Register at D8h, and
2. The ARA Automatic Mask.
The ARA Automatic Mask is a mask that is set in response to a successful ARA read. An ARA read operation
returns the PMBus
returns the PMBus
™
address of the lowest addressed part on the bus that has its SMBA asserted. A successful
ARA read means that THIS part was the one that returned its address. When a part responds to the ARA read, it
releases the SMBA signal. When the last part on the bus that has an SMBA set has successfully reported its
address, the SMBA signal will de-assert.
releases the SMBA signal. When the last part on the bus that has an SMBA set has successfully reported its
address, the SMBA signal will de-assert.
The way that the LM25066I/A releases the SMBA signal is by setting the ARA Automatic mask bit for all fault
conditions present at the time of the ARA read. All status registers will still show the fault condition, but it will not
generate an SMBA on that fault again until the ARA Automatic mask is cleared by the host issuing a Clear Fault
command to this part. This should be done as a routine part of servicing an SMBA condition on a part, even if the
ARA read is not done.
conditions present at the time of the ARA read. All status registers will still show the fault condition, but it will not
generate an SMBA on that fault again until the ARA Automatic mask is cleared by the host issuing a Clear Fault
command to this part. This should be done as a routine part of servicing an SMBA condition on a part, even if the
ARA read is not done.
depicts a schematic version of this flow.
Figure 51. Typical Flow Schematic for SMBA Fault
52
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