Texas Instruments AFE7222 Evaluation Module AFE7222EVM AFE7222EVM Datenbogen
Produktcode
AFE7222EVM
TX controls are
located on this tab
This section controls
power down options
on digital TX chain
Mixing section controls gain, offset,
mixing mode and NCO
This section controls
the TX FIFO
This section controls
auxiliary DACs
RX to TX Loopback
Enable
DCLK
Data
TX Setup
The data coming from the TSW1400 is edge aligned while the
AFE722x expects the serial LVDS data to arrive edge centered. Here
the programmable clock delay can be used to delay the edge-aligned
clock closer towards the center of the data.
AFE722x expects the serial LVDS data to arrive edge centered. Here
the programmable clock delay can be used to delay the edge-aligned
clock closer towards the center of the data.
The table below shows clock delays for the listed DAC sampling rates
that showed proper operation:.
that showed proper operation:.
DAC Sampling Rate
Suitable Clock Delay
130 Msps
0 ps to 900 ps
122.88 Msps
0 ps to 900 ps
100 Msps
0 ps to 1.2 ns
80 Msps
0 ps to 1.8 ns
65 Msps
0 ps to 2.1 ns
40 Msps
0 ps to 2.1 ns
The other portion of the TX setup is located on the Transmit Control tab which includes register access for
the mixing stage, FIFO, Loopback and power options for the digital TX section. The auxiliary DAC
registers are also configured on this tab.
the mixing stage, FIFO, Loopback and power options for the digital TX section. The auxiliary DAC
registers are also configured on this tab.
Figure 13. Transmit Control Tab in TX Setup
17
SLOU362 – February 2013
AFE722x Evaluation Module (AFE722xEVM) User's Guide
Copyright © 2013, Texas Instruments Incorporated