Texas Instruments TPS65810 Evaluation Module TPS65810EVM TPS65810EVM Datenbogen
Produktcode
TPS65810EVM
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FUNCTIONALITY GUIDE – ANALOG TO DIGITAL CONVERTER
ANLG 1
ANLG 2
ADC _ REF
8 CHANNEL
MUX
A/D
CONVERTER
ADC
AGND 2
OUT
A 2
A 2
SYSTEM POWER BUS
ADC
CONTROL
LOGIC
EXTERNAL ANALOG
INPUT VOLTAGE
6 INTERNAL
CHANNELS
C17
4.7 F
4.7 F
m
ANALOG-TO-DIGITAL CONVERTER
Overview
Input Channels
SLVS658B – MARCH 2006 – REVISED FEBRUARY 2007
10 BIT SUCCESSIVE APPROXIMATION ADC
ADC Input Channels
Trigger Mode
Conversion
Converter Mode
Trigger Delay
Wait Time, Multiple
Power Up
Count
Conversions
Default
Internal
External
Range
Min Step
Charge
ANLG1 and
1, 4, 8, 16, 32,
Single, Average,
0-750
µ
s,
50
µ
s
µ
s: 20, 40, 60, 80, 160,
ADC off
GPIB, I
2
C
Current,
ANLG2
64, 128, 256
Find max value,
16 steps
240, 320, 640
driven, Repeat
Thermistor
voltages
Find min value
ms: 1.28, 1.92, 2.56,
temperature,
5.12, 10.24, 15.36, 20.48
IC junction
temperature,
RTC_OUT
voltage, OUT
voltage,
Battery
voltage
voltage
Fixed
Selectable via
Selectable via
Selectable via
Selectable via
Selectable
Selectable
Selectable via I
2
C
internally
I
2
C
I
2
C
I
2
C
I
2
C
via I
2
C
via I
2
C
Figure 46. Required External Components, Recommended Values, External Connections
The TPS65810 has a 10 bit integrated successive approximation A/D, capable of running A/D conversions on
eight distinct channels in a variety of modes. Two of the eight channels are connected to uncommitted pins
ANLG1 and ANLG2, and can be used to convert external voltages. The other six channels monitor system
parameters which are critical to the overall system monitoring. The channel selection is set via I
eight distinct channels in a variety of modes. Two of the eight channels are connected to uncommitted pins
ANLG1 and ANLG2, and can be used to convert external voltages. The other six channels monitor system
parameters which are critical to the overall system monitoring. The channel selection is set via I
2
C.
A dedicated set of I
2
C registers enables configuration of the ADC to perform a conversion cycle with either a
single conversion or a multiple conversions. The ALU generates a data set containing maximum value detection,
minimum value detection and average value calculation for each conversion cycle. Each cycle can be performed
a single time or multiple times.
minimum value detection and average value calculation for each conversion cycle. Each cycle can be performed
a single time or multiple times.
The following channels are available for selection via the I
2
C register ADC_SET bits CHSEL_SET bits:
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