Texas Instruments Evaluation Module for TPS22924B TPS22924BEVM-532 TPS22924BEVM-532 Datenbogen
Produktcode
TPS22924BEVM-532
Test Configurations
5
Test Configurations
5.1
On State Resistance (rON) Test Setup
shows a typical setup for measuring On State Resistance. The voltage drop across the switch is
measured using the sense connections then divided by the current into the load yielding the r
ON
resistance
Figure 1. r
ON
Setup
5.2
Slew Rate Test Setup
shows a test setup for measuring the Slew Rate of the Load Switch. Controlling the ON pin of the
switch with a signal source and then measuring the output with a scope shows the switches ability to
avoid inrush current.
avoid inrush current.
Figure 2. Slew Rate Setup
6
Board Layout, Schematic, and Bill of Materials
This section provides the TPS22924EVM-532 board layout, schematic, and bill of materials.
6.1
Board Layout
For best performance, all traces should be as short as possible. To be most effective, the input and output
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances
may have on normal and short-circuit operation. Using wide traces for V
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances
may have on normal and short-circuit operation. Using wide traces for V
IN
, V
OUT
, and GND helps minimize
the parasitic electrical effects along with minimizing the case to ambient thermal impedance
and
show the board layout for the TPS22924EVM-532 PCB.
3
SLVU456B – May 2011 – Revised May 2013
TPS22924EVM-532
Copyright © 2011–2013, Texas Instruments Incorporated