Texas Instruments CDCE72010EVM - CDCE72010EVM Evaluation Module CDCE72010EVM CDCE72010EVM Datenbogen
Produktcode
CDCE72010EVM
8.5
Configuration for PLL Lock Detect
Configuring the Board
www.ti.com
The external loop filter can be chosen by selecting one from the four available options on the
CDCE72010EVM using the dip switches, SW9 and SW10, located at the back side of the EVM as shown
in the following illustration. The four options are Filter1 = 1 kHz, Filter2 = 520 Hz, Filter3 = 120 Hz, and
Filter4 = 15 Hz.
CDCE72010EVM using the dip switches, SW9 and SW10, located at the back side of the EVM as shown
in the following illustration. The four options are Filter1 = 1 kHz, Filter2 = 520 Hz, Filter3 = 120 Hz, and
Filter4 = 15 Hz.
Figure 2. CDCE72010EVM External Loop Filter Topology
The CDCE72010 PLL lock detect can be chosen on the CDCE72010EVM as either an analog lock detect
or a digital lock detect using the jumper, JP_3_12, located at the back side of the CDCE72010EVM. This
jumper can be configured as shown in the following diagram for either analog or digital lock detect.
or a digital lock detect using the jumper, JP_3_12, located at the back side of the CDCE72010EVM. This
jumper can be configured as shown in the following diagram for either analog or digital lock detect.
1.5-GHz Low-Phase Noise Clock Evaluation Board
12
SLAU250 – May 2008