Texas Instruments Evaluation Module for TPS22929D TPS22929DEVM-661 TPS22929DEVM-661 Datenbogen
Produktcode
TPS22929DEVM-661
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Board Layout, Schematic, and Bill of Materials
5
Board Layout, Schematic, and Bill of Materials
This section provides the TPS2292xxEVM-661 board layout, schematic, and bill of materials.
5.1
Board Layout
For best performance, all traces should be as short as possible. To be most effective, the input and output
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances
may have on normal and short-circuit operation. Using wide traces for V
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances
may have on normal and short-circuit operation. Using wide traces for V
IN
, V
OUT
, and GND helps minimize
the parasitic electrical effects along with minimizing the case to ambient thermal impedance
, and
show the board layout for the TPS2292xxEVM-661 PCB.
Figure 1. Top Assembly Layer
Figure 2. Top Layer
3
SLVU537
–
September 2011
TPS2292xEVM-661
Copyright
©
2011, Texas Instruments Incorporated