Texas Instruments Evaluation Module for TLV809K33 TLV809KEVM-019 TLV809KEVM-019 Datenbogen
Produktcode
TLV809KEVM-019
Power
Supply
Install jumper
on JP1 for
TLV803S only
Power
Supply
Power
Supply
Install jumper
on JP1 for
TLV803S only
V
A
V
Operation
3.2
Connection Setup
Figure 2. Quick Start Connection Setup
1. Connect the power supply and its return connection to J1 and J2 as shown above.
2. An ammeter can be connected in series with the power supply to measure the supply current. A
2. An ammeter can be connected in series with the power supply to measure the supply current. A
voltmeter can also be connected across J1 and J2 to measure the effective voltage at the pins.
3. Connect a voltmeter or an oscilloscope voltage probe across the output pins J3 and J4 to observe and
measure the output voltage.
NOTE:
For TLV803SEVM-019, please verify that jumper on JP1 is present so that pull-up resistor
R1 is connected to VDD and to RESET. If an output voltage different from VDD is desired, a
power supply can be connected to JP1 to pull the RESET pin to a different voltage.
power supply can be connected to JP1 to pull the RESET pin to a different voltage.
4
Operation
This section provides information about the operation of the TLV8xxxEVM and the outputs expected. The
TLV8xxx parts can support supply voltage, V
TLV8xxx parts can support supply voltage, V
DD
, in the range of 2-V to 6-V. No external components are
required. All the devices in this family have a fixed sense-threshold voltage (V
IT
) set by an internal voltage
divider.
4.1
Threshold Voltage, V
IT
During power-on, RESET / RESET is asserted when the supply voltage (V
DD
) becomes higher than 1.1-V.
Thereafter, for active low devices, the supervisory circuit monitors V
DD
and keeps RESET active as long
as V
DD
remains below the threshold voltage, V
IT
. For active high devices, the supervisory circuit keeps
RESET active as long as V
DD
remains above the threshold voltage, V
IT
.
TLV809K and TLV803S (active low RESET output):
•
When V
DD
<
V
IT
, the output across the RESET pins J3 and J4 should be 0-V (low).
•
When V
DD
>
V
IT
, the output across the RESET pins J3 and J4 should equal V
DD
±
0.5-V (high) with no
load.
TLV810S (active high RESET output):
•
When V
DD
<
V
IT
, the output across the RESET pins J3 and J4 should equal V
DD
±
0.5-V (high) with no
load.
•
When V
DD
>
V
IT
, the output across the RESET pins J3 and J4 should be 0-V (low).
3
SLVU461
–
May 2011
TLV8xxxEVM-019 Evaluation Modules
Copyright
©
2011, Texas Instruments Incorporated