Texas Instruments DS100BR410 Low Pwr Quad Ch Repeater with 10.3125 Gbps Eq and De-Emphasis Driver EVM DS100BR410EVK-4/NO DS100BR410EVK-4/NOPB Datenbogen
Produktcode
DS100BR410EVK-4/NOPB
1
2
3
4
5
6
7
8
9
10
11
12
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
36
35
34
33
32
31
30
29
28
27
26
25
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
IN_3-
IN_3+
IN_2-
IN_2+
IN_1-
IN_1+
IN_0-
IN_0+
OUT_3-
OUT_3+
OUT_2-
OUT_2+
OUT_1-
OUT_1+
OUT_0-
OUT_0+
V
DD
V
DD
V
DD
V
DD
GND
GND
GND
GND
V
D
D
V
D
D
G
N
D
G
N
D
BST
_
1
BST_
0
C
S
SD
C
SD
A
O
O
B
_
D
IS
V
D
D
SD
0
EN
0
SD
1
EN
1
SD
2
EN
2
SD
3
EN
3
R
ES
BST_
2
VO
D
_
SEL
D
E_
SEL
PI
N
_MO
D
E
DS100BR410
TOP VIEW
DAP = GND
SNLS326B – OCTOBER 2010 – REVISED APRIL 2013
Connection Diagram
Pin Descriptions
Pin Name
Pin #
I/O, Type
(1)
Description
HIGH SPEED DIFFERENTIAL I/O
IN_0+
1
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100
Ω
IN_0–
2
terminating resistor connects IN_0+ to IN_0-.
IN_1+
4
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100
Ω
IN_1–
5
terminating resistor connects IN_1+ to IN_1-.
IN_2+
8
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100
Ω
IN_2–
9
terminating resistor connects IN_2+ to IN_2-.
IN_3+
11
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100
Ω
IN_3–
12
terminating resistor connects IN_3+ to IN_3-.
OUT_0+
36
O, CML
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100
Ω
OUT_0–
35
terminating resistor connects OUT_0+ to OUT_0-.
OUT_1+
33
O, CML
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100
Ω
OUT_1–
32
terminating resistor connects OUT_1+ to OUT_1-.
OUT_2+
29
O, CML
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100
Ω
OUT_2–
28
terminating resistor connects OUT_2+ to OUT_2-.
OUT_3+
26
O, CML
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100
Ω
OUT_3–
25
terminating resistor connects OUT_3+ to OUT_3-.
2.5V LVCMOS CONTROL PINS
BST_2
37
I, LVCMOS
BST_2, BST_1, and BST_0 select the equalizer boost level for all channels.
BST_1
14
BST_2 and BST_1 are internally pulled high.
BST_0
23
BST_0 is internally pulled low. See
EN0
44
I, LVCMOS
Enable channel n input.
EN1
42
When held High, normal operation is selected.
EN2
40
When held Low, standby mode is selected.
EN3
38
EN is internally pulled High.
(1)
Note: I = Input
O = Output, LVCMOS pins are 2.5 V levels only, only SMBus pins SDA, SDC and CS are 3.3V tolerant.
2
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