Texas Instruments TPS23752 Evaluation Module TPS23752EVM-145 TPS23752EVM-145 Datenbogen
Produktcode
TPS23752EVM-145
Description
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Description
The EVM enables full evaluation of the TPS23752 device. Refer to the schematics shown in
and
. Ethernet power is applied from J1 to T1 and is dropped to the diode bridges (D1/D2/D7/D8 or
D3/D4/D9/D10) from the T1 center taps. The series R-C circuits from each center tap help balance the
Ethernet cable impedance and are critical for ESD and EMI/EMC performance. These circuits are
terminated at TP7 (EGND) through the high-voltage capacitor, C10. At the output of the diode bridges is
the EMI/EMC filter and transient protection for the TPS23752.
Ethernet cable impedance and are critical for ESD and EMI/EMC performance. These circuits are
terminated at TP7 (EGND) through the high-voltage capacitor, C10. At the output of the diode bridges is
the EMI/EMC filter and transient protection for the TPS23752.
Input power can also be applied at J3 from a dc source. EMI/EMC filtering is provided at this connector as
well and diode D5 provides reverse-voltage protection. R5 and R10 provide a threshold for the TPS23752
APD pin so that the TPS23752 internal MOSFET is disabled when the voltage at J3 is above
approximately 18 V. This ensures that the adapter has priority over the PSE source.
well and diode D5 provides reverse-voltage protection. R5 and R10 provide a threshold for the TPS23752
APD pin so that the TPS23752 internal MOSFET is disabled when the voltage at J3 is above
approximately 18 V. This ensures that the adapter has priority over the PSE source.
Below the PoE diode bridges in
are four opto-isolated circuits. U1, U2, U3, and associated
circuits support the sleep or low-power mode of the TPS23752. The U4 circuit indicates when an adapter
or type 2 PoE source is present.
or type 2 PoE source is present.
The TPS23752 (U5) PD and dc/dc converter circuitry is shown in
. R23 provides the detection
signature and R26 provides the classification (class 4) signature. To the right of the U5 is the switched
side of the PD controller. The TPS23752 RTN pin provides inrush limited turn on and charge of the bulk
capacitor, C16. During inrush, the TPS23752 dc/dc controller is disabled.
side of the PD controller. The TPS23752 RTN pin provides inrush limited turn on and charge of the bulk
capacitor, C16. During inrush, the TPS23752 dc/dc controller is disabled.
The dc/dc converter is a driven synchronous, isolated flyback topology. The flyback converter operates in
either variable-frequency (VFO) or pulse-width modulated (PWM) modes depending on output loading to
boost wide load range efficiency. The primary (Q5) and secondary (Q3) switching MOSFETs are driven
from the U5 GATE pin. MOSFET gate-drive buffering and phasing is provided by Q6/D16/R32 (primary)
and T3/Q4/D18/R38 (secondary), respectively. In addition to Q3, D17 provides secondary side rectification
when the converter is in VFO mode. R25/D15/C27/C29 form the auxiliary 12-V output for the U5 dc/dc
controller and D13/R22/C19 provide peak voltage clamp protection for Q5.
either variable-frequency (VFO) or pulse-width modulated (PWM) modes depending on output loading to
boost wide load range efficiency. The primary (Q5) and secondary (Q3) switching MOSFETs are driven
from the U5 GATE pin. MOSFET gate-drive buffering and phasing is provided by Q6/D16/R32 (primary)
and T3/Q4/D18/R38 (secondary), respectively. In addition to Q3, D17 provides secondary side rectification
when the converter is in VFO mode. R25/D15/C27/C29 form the auxiliary 12-V output for the U5 dc/dc
controller and D13/R22/C19 provide peak voltage clamp protection for Q5.
Output voltage feedback is provided with the U7 and associated error amplifier (U8) circuitry. R46
provides a means for error injection when measuring the frequency response of the converter. This
feedback circuit drives the U5 CTL pin providing a voltage proportional to the output load current. The
voltage on the CTL pin can also detect the desired mode transition point by comparing this with the
voltage on the SRT pin (set by R31 and R35). As output load decreases, the CTL pin voltage also
decreases. When CTL crosses the transition point (going into VFO mode), the converter disables Q3 and
allows D17 to rectify. This is accomplished with the U5 SRD pin, U6, and Q7/Q8/Q9. In VFO mode, Q9 is
ON and Q8 is OFF. This effectively extinguishes the Q3 gate drive allowing D17 to rectify. When output
load increases, the converter goes back to PWM mode and allows Q3 to provide rectification.
provides a means for error injection when measuring the frequency response of the converter. This
feedback circuit drives the U5 CTL pin providing a voltage proportional to the output load current. The
voltage on the CTL pin can also detect the desired mode transition point by comparing this with the
voltage on the SRT pin (set by R31 and R35). As output load decreases, the CTL pin voltage also
decreases. When CTL crosses the transition point (going into VFO mode), the converter disables Q3 and
allows D17 to rectify. This is accomplished with the U5 SRD pin, U6, and Q7/Q8/Q9. In VFO mode, Q9 is
ON and Q8 is OFF. This effectively extinguishes the Q3 gate drive allowing D17 to rectify. When output
load increases, the converter goes back to PWM mode and allows Q3 to provide rectification.
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SLVU753 – July 2012
TPS23752EVM-145: Evaluation Module for TPS23752
Copyright © 2012, Texas Instruments Incorporated