Texas Instruments Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.9 GHz VCO LMK04808BEVAL/NOPB LMK04808BEVAL/NOPB Datenbogen
Produktcode
LMK04808BEVAL/NOPB
L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
27
Clock Outputs Tab
Figure 9: Clock Outputs tab
The Clock Outputs tab allows the user to control the output channel blocks, including:
Clock Group Source from either VCO or OSCin (via OSC Mux1 and OSC Mux2)
Channel Powerdown (affects digital and analog delay, clock divider, and buffer blocks)
Digital Delay value and Half Step
Clock Divide value
Analog Delay value and Delay bypass/enable (per output)
Clock Output format (per output)
Channel Powerdown (affects digital and analog delay, clock divider, and buffer blocks)
Digital Delay value and Half Step
Clock Divide value
Analog Delay value and Delay bypass/enable (per output)
Clock Output format (per output)
This tab also allows the user to select the VCO Divider value (2 to 8). Note that the total PLL2
N divider value is the product of the VCO Divider value and the PLL N Prescaler and N Counter