Texas Instruments Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.9 GHz VCO LMK04808BEVAL/NOPB LMK04808BEVAL/NOPB Datenbogen
Produktcode
LMK04808BEVAL/NOPB
L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
30
VCO Frequency (MHz)
n/a
The VCO Frequency should be the OSCin
frequency, except when operating in Dual
PLL with 0-delay feedback. This value is
calculated as:
VCO Freq (OSCin freq) = PLL1 PDF *
PLL1_N.
In Dual PLL mode with 0-delay feedback,
the VCO frequency should be set to the
feedback clock input frequency. See the
section Setting the PLL1 VCO Frequency
and PLL2 Reference Frequency for details.
frequency, except when operating in Dual
PLL with 0-delay feedback. This value is
calculated as:
VCO Freq (OSCin freq) = PLL1 PDF *
PLL1_N.
In Dual PLL mode with 0-delay feedback,
the VCO frequency should be set to the
feedback clock input frequency. See the
section Setting the PLL1 VCO Frequency
and PLL2 Reference Frequency for details.
R Counter
PLL1_R
PLL1 R Counter value (1 to 16383).
N Counter
PLL1_N
PLL1 N Counter value (1 to 16383).
Phase Detector Polarity
PLL1_CP_POL
PLL1 Phase Detector Polarity.
Click on the polarity sign to toggle polarity
“+” or “–”.
Click on the polarity sign to toggle polarity
“+” or “–”.
Charge Pump Gain
PLL1_CP_GAIN
PLL1 Charge Pump Gain.
Left-click/right-click to increase/decrease
charge pump gain (100, 200, 400, 1600 uA).
Left-click/right-click to increase/decrease
charge pump gain (100, 200, 400, 1600 uA).
Charge Pump State
PLL1_CP_TRI
PLL1 Charge Pump State.
Click to toggle between Active and Tri-State.
Click to toggle between Active and Tri-State.
Setting the PLL1 VCO Frequency and PLL2 Reference Frequency
When operating in Dual PLL mode without 0-delay feedback, the VCO frequency value on the
PLL1 tab must match the Reference Oscillator (OSCin) frequency value on the PLL2 tab;
otherwise, the one or both PLLs may be out of lock. Updating the Reference Oscillator
frequency on the PLL2 tab will automatically update the value of OSCin_FREQ on the
Bits/Pins tab.
However, when operating in Dual PLL mode with 0-delay feedback, it may be valid for the VCO
frequency value on the PLL1 tab to be different from the Reference Oscillator (OSCin)
frequency value on the PLL2 tab. This is because in 0-delay mode, the PLL1 feedback clock is
taken from an output clock instead of the OSCin clock. For example, if the CLKin frequency (to
PLL1_R) is 30.72 MHz, the 0-delay feedback clock frequency (to PLL1_N) is 30.72 MHz, and
the VCXO frequency is 122.88 MHz, then the VCO frequency value on the PLL1 tab should be
30.72 MHz (0-delay feedback frequency) and the Reference Oscillator frequency value on the
PLL2 tab should be 122.88 MHz (VCXO frequency). Because of the mismatched frequencies, a
warning message will indicate this condition on the Clock Outputs tab but may be disregarded
in a case like this.
PLL1 tab must match the Reference Oscillator (OSCin) frequency value on the PLL2 tab;
otherwise, the one or both PLLs may be out of lock. Updating the Reference Oscillator
frequency on the PLL2 tab will automatically update the value of OSCin_FREQ on the
Bits/Pins tab.
However, when operating in Dual PLL mode with 0-delay feedback, it may be valid for the VCO
frequency value on the PLL1 tab to be different from the Reference Oscillator (OSCin)
frequency value on the PLL2 tab. This is because in 0-delay mode, the PLL1 feedback clock is
taken from an output clock instead of the OSCin clock. For example, if the CLKin frequency (to
PLL1_R) is 30.72 MHz, the 0-delay feedback clock frequency (to PLL1_N) is 30.72 MHz, and
the VCXO frequency is 122.88 MHz, then the VCO frequency value on the PLL1 tab should be
30.72 MHz (0-delay feedback frequency) and the Reference Oscillator frequency value on the
PLL2 tab should be 122.88 MHz (VCXO frequency). Because of the mismatched frequencies, a
warning message will indicate this condition on the Clock Outputs tab but may be disregarded
in a case like this.