Texas Instruments Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.9 GHz VCO LMK04808BEVAL/NOPB LMK04808BEVAL/NOPB Datenbogen
Produktcode
LMK04808BEVAL/NOPB
L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
35
HOLD_DLD_CNT
In HOLDOVER mode, wait for this many clocks of
PLL1 PDF within the tolerances of PLL1_WND
_SIZE before exiting holdover mode.
PLL1 PDF within the tolerances of PLL1_WND
_SIZE before exiting holdover mode.
DAC_CLK_DIV
DAC update clock is the PLL1 phase detector
divided by this divisor. For proper operation, DAC
update clock rate should be <= 100 kHz.
DAC update rate = PLL1 phase detector frequency /
DAC_CLK_DIV
divided by this divisor. For proper operation, DAC
update clock rate should be <= 100 kHz.
DAC update rate = PLL1 phase detector frequency /
DAC_CLK_DIV
EN_MAN_DAC
Enables manual DAC mode and set DAC voltage
when in holdover.
when in holdover.
MAN_DAC
Sets the value for the DAC when EN_MAN_DAC
is 1 and holdover is engaged. Readback from this
register is the current DAC value whether in
manual DAC mode or DAC tracking mode
is 1 and holdover is engaged. Readback from this
register is the current DAC value whether in
manual DAC mode or DAC tracking mode
DAC_LOW_TRIP
Value from GND in ~50mV steps at which a clock
switch event is generated. If Holdover mode is
enabled, it will be engaged upon the clock switch
event.
NOTE: EN_VTUNE_RAIL_DET must be enabled
for this to be valid.
switch event is generated. If Holdover mode is
enabled, it will be engaged upon the clock switch
event.
NOTE: EN_VTUNE_RAIL_DET must be enabled
for this to be valid.
DAC_HIGH_TRIP
Value from VCC (3.3V) in ~50mV steps at which
clock switch event is generated. If Holdover mode
is enabled, it will be engaged upon the clock switch
event.
NOTE: EN_VTUNE_RAIL_DET must be enabled
for this to be valid.
clock switch event is generated. If Holdover mode
is enabled, it will be engaged upon the clock switch
event.
NOTE: EN_VTUNE_RAIL_DET must be enabled
for this to be valid.
P
LL1
PLL1_WND_SIZE
If the phase error between the PLL1 reference and
feedback clocks is less than specified time, then the
PLL1 lock counter increments.
NOTE: Final lock detect valid signal is determined
when the PLL1 lock counter meets or exceeds the
PLL1_DLD_CNT value.
feedback clocks is less than specified time, then the
PLL1 lock counter increments.
NOTE: Final lock detect valid signal is determined
when the PLL1 lock counter meets or exceeds the
PLL1_DLD_CNT value.
PLL1_DLD_CNT
The reference and feedback of PLL1 must be within
the window of phase error as specified by
PLL1_WND_SIZE for this many cycles before
PLL1 digital lock detect is asserted.
the window of phase error as specified by
PLL1_WND_SIZE for this many cycles before
PLL1 digital lock detect is asserted.
CLKinX_PreR_DIV
The PreR dividers divide the CLKinX reference
before the PLL1_R divider.
Unique divides on individual CLKinX signals
allows switchover from one clock input to another
clock input without needing to reprogram the
PLL1_R divider to keep the device in lock.
before the PLL1_R divider.
Unique divides on individual CLKinX signals
allows switchover from one clock input to another
clock input without needing to reprogram the
PLL1_R divider to keep the device in lock.
PLL1_N_DLY
N delay causes clock outputs to lead clock input
when in a 0-delay mode. Increasing the N delay
value increases the output phase lead relative to the
input.
when in a 0-delay mode. Increasing the N delay
value increases the output phase lead relative to the
input.