Texas Instruments Test System for BQ27000 BQ27200 Based Circuit Boards BQ27X00-TESTER BQ27X00-TESTER Datenbogen
Produktcode
BQ27X00-TESTER
www.ti.com
Relative State-of-Charge (RSOC) — Address 0x0B
Nominal Available Capacity Registers (NACL/NACH) — Address 0x0C/0x0D
Discharge Rate Compensated Available Capacity Registers (CACDL/CACDH) — Address
Temperature Compensated CACD Registers (CACTL/CACTH) — Address 0x10/0x11
SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006
CI
Capacity Inaccurate flag. A 1 indicates that the firmware has not been through a valid learning cycle
and is basing all calculations on initial design values programmed into EEPROM or that there have
been at least 32 cycle-count increments since the last learning cycle. This bit is cleared only on a
LMD update following a learning cycle. This bit is set to 1 on a full reset. The previous value is
retained if no RAM corruption is detected after a reset.
and is basing all calculations on initial design values programmed into EEPROM or that there have
been at least 32 cycle-count increments since the last learning cycle. This bit is cleared only on a
LMD update following a learning cycle. This bit is set to 1 on a full reset. The previous value is
retained if no RAM corruption is detected after a reset.
CALIP
Calibration-In-Progress flag. This flag is set whenever an automatic or commanded offset
calibration measurement is being made. This bit is set to 0 on all resets.
calibration measurement is being made. This bit is set to 0 on all resets.
VDQ
Valid Discharge flag. A 1 indicates that the bqJUNIOR has met all necessary requirements for the
firmware to learn the battery capacity. This bit clears to 0 on a LMD update or condition that
disqualifies a learning cycle. This bit is cleared to 0 on all resets.
firmware to learn the battery capacity. This bit clears to 0 on a LMD update or condition that
disqualifies a learning cycle. This bit is cleared to 0 on all resets.
EDV1
First End-of-Discharge-Voltage flag. A 1 indicates that voltage on the BAT pin is less than or equal
to the EDV1 voltage programmed in EEPROM and the battery has less than or equal to 6.25% of
LMD capacity remaining. LMD updates immediately if the VDQ bit is set when this bit transitions
from 0 to 1. This bit is cleared to 0 on all resets.
to the EDV1 voltage programmed in EEPROM and the battery has less than or equal to 6.25% of
LMD capacity remaining. LMD updates immediately if the VDQ bit is set when this bit transitions
from 0 to 1. This bit is cleared to 0 on all resets.
EDVF
Final End-of-Discharge-Voltage flag. A 1 indicates that the battery has discharged to the empty
capacity threshold. This bit is cleared to 0 on all resets.
capacity threshold. This bit is cleared to 0 on all resets.
The host system has read-only access to this register.
RSOC reports the nominal available capacity as a percentage of the last measured discharge value (LMD). The
equation is:
equation is:
RSOC (%) = 100 * NAC/LMD
The host system has read-only access to this register.
This register pair increments during charge (V
SRP
> V
SRN
) if Voltage > EDVF threshold and decrements during
discharge (V
SRP
< V
SRN
). The NAC registers are cleared by a reset if RAM corruption is detected. The register
value is retained after a reset if RAM corruption is not detected. The host system has read-only access to this
register pair. NAC is reported in units of 3.57 µVh per count.
register pair. NAC is reported in units of 3.57 µVh per count.
0x0E/0x0F
This register pair reports available capacity in the battery, compensated for discharge rate. This register pair
follows NAC during charge and is reduced from NAC during discharge by an amount computed from AI and the
discharge rate compensation value programmed into EEPROM. CACD is not allowed to increase while
discharging, so that if the discharge rate decreases, the available capacity does not increase. CACD equals NAC
if the CHGS bit is 1. If CHGS is 0, CACD is the smaller of the previous and new computed values. The host
system has read-only access to this register pair. CACD is reported in units of 3.57 µVh per count.
follows NAC during charge and is reduced from NAC during discharge by an amount computed from AI and the
discharge rate compensation value programmed into EEPROM. CACD is not allowed to increase while
discharging, so that if the discharge rate decreases, the available capacity does not increase. CACD equals NAC
if the CHGS bit is 1. If CHGS is 0, CACD is the smaller of the previous and new computed values. The host
system has read-only access to this register pair. CACD is reported in units of 3.57 µVh per count.
This register pair reports available capacity in the battery, compensated for both discharge rate and temperature.
This register pair follows CACD during both charge and discharge unless the temperature has fallen below the
threshold programmed into EEPROM. Once the temperature falls below the programmed threshold, the CACT
value is reduced from CACD by an amount computed from ILMD and the temperature compensation constants
programmed into EEPROM. This is the base capacity value used to calculate time-to-empty and compensated
state-of-charge. The host system has read-only access to this register pair. CACT is reported in units of 3.57 µVh
per count.
This register pair follows CACD during both charge and discharge unless the temperature has fallen below the
threshold programmed into EEPROM. Once the temperature falls below the programmed threshold, the CACT
value is reduced from CACD by an amount computed from ILMD and the temperature compensation constants
programmed into EEPROM. This is the base capacity value used to calculate time-to-empty and compensated
state-of-charge. The host system has read-only access to this register pair. CACT is reported in units of 3.57 µVh
per count.
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