Texas Instruments Test System for BQ27000 BQ27200 Based Circuit Boards BQ27X00-TESTER BQ27X00-TESTER Datenbogen
Produktcode
BQ27X00-TESTER
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Discharge Rate Compensation Constants (DCOMP) — Address 0x7E
Temperature Compensation Constants (TCOMP) — Address 0x7F
SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006
The user can optionally use this byte in the EEPROM as an identification byte. If so used, the user should ignore
the values in MLI and MLTTE registers.
the values in MLI and MLTTE registers.
This register is used to set the compensation coefficients for discharge rate. These coefficients are applied to the
nominal available charge to more accurately predict capacity at high discharge rates.
nominal available charge to more accurately predict capacity at high discharge rates.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME
DCGN[5]
DCGN[4]
DCGN[3]
DCGN[2]
DCGN[1]
DCGN[0]
DCOFF[1]
DCOFF[0]
DCGN[5:0]
Discharge rate compensation gain. Used to set the slope of the discharge rate capacity
compensation. The gain factor adjustment is in increments of 0.39% of discharge current in excess
of the DCOFF value. The equation for programming the value is:
compensation. The gain factor adjustment is in increments of 0.39% of discharge current in excess
of the DCOFF value. The equation for programming the value is:
DCGN[5:0] = 2.56 * Design discharge compensation gain %
DCOFF[1:0] These bits set the discharge threshold of compensating the nominal available charge for discharge
rate. The threshold is set as listed in
.
Table 5. Discharge Rate Compensation Thresholds
DCOFF[1]
DCOFF[0]
DCOFF Threshold
0
0
0
0
1
C/2 (ILMD*256
÷
2)
1
0
C/4 (ILMD*256
÷
4)
1
1
C/8 (ILMD*256
÷
8)
Discharge compensation, DCMP, is computed from these coefficients as follows:
DCMP = DCGN(AI-DCOFF)/256
where DCMP
≥
0. The CACD register then takes on the value:
CACD = NAC – (DCMP – LMDCMP), if DCMP > LMDCMP or
CACD = NAC, if DCMP
≤
LMDCOMP
where LMDCMP is the value of DCMP when the last LMD value was learned. This allows the compensation for
CACD to adapt as the LMD value is learned.
CACD to adapt as the LMD value is learned.
If PKCFG[1] = 1, the device assumes a fixed value of 0x42 for DCOMP, giving a discharge rate compensation
gain of 6.25% with a compensation threshold of C/4. This frees the EEPROM location of 0x7E for use as a
programmable identification byte.
gain of 6.25% with a compensation threshold of C/4. This frees the EEPROM location of 0x7E for use as a
programmable identification byte.
This register is used to set the compensation coefficients for temperature. These coefficients are applied to the
discharge rate compensated available charge to more accurately predict capacity available at cold temperature.
discharge rate compensated available charge to more accurately predict capacity available at cold temperature.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TCGN[3]
TCGN[2]
TCGN[1]
TCGN[0] NAME TOFF[3]
TOFF[2]
TOFF[1]
TOFF[0]
TCGN[3:0]
Temperature compensation gain. Used to set the slope of the compensation as a percentage of
Design Capacity (DC) decrease per
Design Capacity (DC) decrease per
°
C. The equation for programming the value is:
TCGN[3:0] = 10.24 * Design Temp Compensation Gain % DC/
°
C
TOFF[3:0]
Temperature compensation offset. Used to set the offset of the compensation. The temperature
threshold is also used as the cold temperature disqualification for a learning cycle. The equation for
programming the value is:
threshold is also used as the cold temperature disqualification for a learning cycle. The equation for
programming the value is:
TOFF[3:0] = Design Temp Compensation Offset (
°
K) – 273
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