Texas Instruments XILINXPWR-080 Power Management Evaluation Module for Xilinx FPGAs XILINXPWR-080 XILINXPWR-080 Datenbogen

SLVL005 

XILINXPWR-080 (HPA-080) 

Dual Linear Regulator Power Management Solution Providing up to 850 mA from V

IN

 = 

3.3 V  

SUPPORTS : 
 

Spartan™-3 Design 2 (PR214) - 

http://focus.ti.com/lit/ml/slva175/slva175.pdf 

 
FEATURES: 
 

Dual channel low-dropout (LDO) linear regulator in thermally enhanced 
PowerPAD

T M

 package saves cost and space. 

Linear regulators start- up fast, allowing large in-rush currents for charging 
decoupling capacitors and FPGA start-up.  The current draw on the input power 
supply is minimized by the use of the optional: 

o

  External SVS, U1, which monitors the input rail and prevents the regulator 

from enabling until the input bulk capacitors (not shown in the schematic) 
are fully charged.  

o

  Soft-start circuit consisting of the external NMOS transistor Q1 and 

supporting passive components to provide 10 ms rise time for V

CCINT

  

§

§

Soft-start circuit (Q1) forces sequencing of V

CCAUX

, then V

CCINT,

 

with EN1 and EN2 tied together. 

The design meets Xilinx’s V

CCINT

 start-up profile requirements, where applicable, 

including monotonic voltage ramp, in-rush current and power voltage ramp time 
requirements.  

 
IMPORTANT WEB LINKS: 
 

Link to the TI home page for Xilinx FPGA power management solutions at 
http://www.ti.com/xilinxfpga for more information and other reference designs. 

Link to datasheets at http://focus.ti.com/lit/ds/symlink/TPS70402.pdf and 
http://focus.ti.com/lit/ds/symlink/tlc7733.pdf.  

Link to application note SLVA118 http://focus.ti.com/lit/an/slva118/slva118.pdf 
to explore the thermal considerations when using linear regulators.  

Link to application note SLVA156 http://focus.ti.com/lit/an/slva156/slva156.pdf 
for more details on the soft-start circuit. 

Link to application note SLVA159 
http://focus.ti.com/lit/an/slva159a/slva159a.pdf when using 3.3-V JTAG ports. 

 
IMPLEMENTATION NOTES: 
 

Sequencing: Although Xilinx FPGAs do NOT require it, this reference design 
employs sequencing. This practice is consistent with good power supply design 
and prevents the input power supply from being pulled down due to supporting 
in-rush currents for charging large capacitive loads.