Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Datenbogen
Produktcode
PIC18F65J15-I/PT
© 2009 Microchip Technology Inc.
DS39663F-page 139
PIC18F87J10 FAMILY
TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
RE6/AD14/
P1B
P1B
RE6
0
O
DIG
LATE<6> data output.
1
I
ST
PORTE<6> data input.
AD14
(3)
x
O
DIG
External memory interface, address/data bit 14 output.
(2)
x
I
TTL
External memory interface, data bit 14 input.
(2)
P1B
(1)
0
O
DIG
ECCP1 Enhanced PWM output, Channel B; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE7/AD15/
ECCP2/P2A
ECCP2/P2A
RE7
0
O
DIG
LATE<7> data output.
1
I
ST
PORTE<7> data input.
AD15
(3)
x
O
DIG
External memory interface, address/data bit 15 output.
(2)
x
I
TTL
External memory interface, data bit 15 input.
(2)
ECCP2
(4)
0
O
DIG
CCP2 compare output and CCP2 PWM output; takes priority over
port data.
port data.
1
I
ST
CCP2 capture input.
P2A
(4)
0
O
DIG
ECCP2 Enhanced PWM output, Channel A; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
PORTG
RDPU
REPU
RJPU
(1)
RG4
RG3
RG2
RG1
RG0
Legend: Shaded cells are not used by PORTE.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
TABLE 11-11: PORTE FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1:
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
2:
External memory interface I/O takes priority over all other digital and PSP I/O.
3:
Available on 80-pin devices only.
4:
Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (all devices in Microcontroller mode).