Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Datenbogen
Produktcode
PIC18F65J15-I/PT
PIC18F87J10 FAMILY
DS39663F-page 142
© 2009 Microchip Technology Inc.
11.8
PORTG, TRISG and
LATG Registers
LATG Registers
PORTG is a 5-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTG pin an output (i.e.,
put the contents of the output latch on the selected pin).
All pins on PORTG are digital only and tolerate
voltages up to 5.5V.
The Output Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register read and write the latched output value for
PORTG.
PORTG is multiplexed with EUSART2 functions
(Table 11-15). PORTG pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
sponding Data Direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTG pin an output (i.e.,
put the contents of the output latch on the selected pin).
All pins on PORTG are digital only and tolerate
voltages up to 5.5V.
The Output Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register read and write the latched output value for
PORTG.
PORTG is multiplexed with EUSART2 functions
(Table 11-15). PORTG pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
Although the port is only five bits wide, PORTG<7:5>
bits are still implemented. These are used to control the
weak pull-ups on the I/O ports associated with the
external memory bus (PORTD, PORTE and PORTJ).
Setting these bits enables the pull-ups. Since these are
control bits and are not associated with port I/O, the
corresponding TRISG and LATG bits are not
implemented.
bits are still implemented. These are used to control the
weak pull-ups on the I/O ports associated with the
external memory bus (PORTD, PORTE and PORTJ).
Setting these bits enables the pull-ups. Since these are
control bits and are not associated with port I/O, the
corresponding TRISG and LATG bits are not
implemented.
EXAMPLE 11-7:
INITIALIZING PORTG
CLRF
PORTG
; Initialize PORTG by
; clearing output
; data latches
; clearing output
; data latches
CLRF
LATG
; Alternate method
; to clear output
; data latches
; to clear output
; data latches
MOVLW
04h
; Value used to
; initialize data
; direction
; initialize data
; direction
MOVWF
TRISG
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
; RG2 as input
; RG4:RG3 as inputs