Texas Instruments TPS79328YEQEVM Evaluation Module for TPS79328 in Chipscale Package TPS79328YEQEVM TPS79328YEQEVM Datenbogen
Produktcode
TPS79328YEQEVM
Layout
3-2
3.1
Layout
Board layout is critical for reliable and easy to assemble chip-scale de-
signs. Figure 3−1, Figure 3−2, and Figure 3−3 show the board layout for
the TPS793xxYEQEVM printed wiring board (PWB). Careful attention
should be given to the routing to the chip-scale IC lands. Refer to the Na-
noStar
signs. Figure 3−1, Figure 3−2, and Figure 3−3 show the board layout for
the TPS793xxYEQEVM printed wiring board (PWB). Careful attention
should be given to the routing to the chip-scale IC lands. Refer to the Na-
noStar
Wafer Chip-Scale Package Design Guide for specific layout guide-
lines.
Figure 3−1. Assembly Layer
Figure 3−2. Top Layer Routing
Figure 3−3. Bottom Layer Routing