Texas Instruments Evaluation Board for the LP38502 LP38502TJ-ADJEV LP38502TJ-ADJEV Datenbogen
Produktcode
LP38502TJ-ADJEV
Feedforward Capacitor C2
4
Feedforward Capacitor C2
The PCB layout includes a location for C2, which is a feedforward capacitor connected across R1. If the
data sheet guidelines are followed, and R2 does not exceed 10 k
data sheet guidelines are followed, and R2 does not exceed 10 k
Ω
, C2 is not required and has no effect
on performance. The internal compensation is such that an internal zero provides more than adequate
phase margin so external compensation is never needed.
phase margin so external compensation is never needed.
However, if the value of R2 is increased above 10 k
Ω
, the effect of the internal zero gradually diminishes
and the phase margin is reduced. At an R2 value of approximately 50 k
Ω
, the phase margin will be low
enough that instability may occur. In such cases, some of the lost phase margin can be regained by
placing a capacitor at C2. Although it is sometimes possible to regain adequate phase margin this way, it
is recommended that the data sheet guidelines be followed and R2 not exceed 10 k
placing a capacitor at C2. Although it is sometimes possible to regain adequate phase margin this way, it
is recommended that the data sheet guidelines be followed and R2 not exceed 10 k
Ω
(so C2 is never
required).
5
Power Dissipation
The power dissipated within the regulator IC is given by:
P
D
= I
L
(V
IN
- V
OUT
)
(2)
Where:
P
D
is the power dissipated in the IC regulator U1.
I
L
is the load current.
V
IN
is the value of V
IN
measured at TP2 (not at J1).
V
OUT
is the value of V
OUT
measured at TP5 (not at J4).
The thermal resistance of U1 from junction to ambient can be assumed to be approximately 30°C/W for
this assembly. That means that the junction temperature will rise about 30°C above ambient for each Watt
of power dissipated within the IC.
this assembly. That means that the junction temperature will rise about 30°C above ambient for each Watt
of power dissipated within the IC.
The parametric specifications of the IC are for a maximum junction temperature of 125°C, and the
maximum allowable junction temperature is 150°C. This limits maximum usable power dissipation for this
package to approximately 3.3W. If power dissipation exceeds this (and the junction temperature
approaches 150°C) the part may go into thermal shutdown.
maximum allowable junction temperature is 150°C. This limits maximum usable power dissipation for this
package to approximately 3.3W. If power dissipation exceeds this (and the junction temperature
approaches 150°C) the part may go into thermal shutdown.
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AN-1782 LP38502TJ-ADJ Evaluation Board
SNVA321A – January 2008 – Revised April 2013
Copyright © 2008–2013, Texas Instruments Incorporated