Texas Instruments Evaluation Module for TLV62065 TLV62065EVM-719 TLV62065EVM-719 Datenbogen
Produktcode
TLV62065EVM-719
J3
J4
J2
J5
J1
J6
JP2
PWM
MODE
PFM
JP1
ON
EN
OFF
VIN
GND
VOUT
GND
S-
+
S+
-
S-
TLV62065EVM-719
DC
Power Supply
Load
Oscilloscope
-
+
S+
Test Configuration
www.ti.com
3.1.8
JP2, MODE
This jumper enables/disables the power-saving mode under light loads. Shorting jumper JP2 between the
center pin and PWM disables the power-saving mode. If the power-save mode is disabled, the converter
operates in forced PWM mode over the entire load current range. Shorting the jumper between the center
pin and PFM enables the power-saving mode. The device operates in power-saving mode under light load
conditions. See the TLV62065 data sheet (
center pin and PWM disables the power-saving mode. If the power-save mode is disabled, the converter
operates in forced PWM mode over the entire load current range. Shorting the jumper between the center
pin and PFM enables the power-saving mode. The device operates in power-saving mode under light load
conditions. See the TLV62065 data sheet (
) for a detailed description of this configuration. A 1-
M
Ω
pulldown resistor is connected between GND and MODE. By removing JP2, the converter operates in
power-saving mode under light-load conditions.
3.1.9
J7, VOUT (SMA)
This SMA connector is connected to the output voltage of the TLV62065. It can be used to easily analyze
the noise spectrum of the output voltage with a spectrum analyzer. By default, J7 is not assembled on the
EVM.
the noise spectrum of the output voltage with a spectrum analyzer. By default, J7 is not assembled on the
EVM.
4
Test Configuration
4.1
Hardware Setup
illustrates a typical hardware test configuration.
Figure 2. Hardware Board Connection
4
TLV62065EVM-719
SLVU424 – December 2010
© 2010, Texas Instruments Incorporated