Texas Instruments Evaluation Module for TPS657051 TPS657051EVM-522 TPS657051EVM-522 Datenbogen
Produktcode
TPS657051EVM-522
Connector and Test Point Descriptions
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4
Connector and Test Point Descriptions
4.1
Input/Output Connectors
4.1.1
J1 – VLDO
This header is the positive output of the low-dropout (LDO) linear regulator. The default output voltage of
the LDO is 3 V (TPS657051) and 2.8 V (TPS657052). The LDO is capable of sourcing up to 200-mA. A
load can be connected between J1 and J3 (GND).
the LDO is 3 V (TPS657051) and 2.8 V (TPS657052). The LDO is capable of sourcing up to 200-mA. A
load can be connected between J1 and J3 (GND).
This header is the positive connection to the input power supply. The power supply must be connected
between J1 and J2 (GND). Twist the leads to the input supply, and keep them as short as possible. The
input voltage has to be between 4.35 V and 6 V.
between J1 and J2 (GND). Twist the leads to the input supply, and keep them as short as possible. The
input voltage has to be between 4.35 V and 6 V.
4.1.2
J2 – S+/S–
J2 S+/S– is the sense connection for the output of the LDO. Connect a voltmeter, sense connection of an
electronic load, or oscilloscope to this header.
electronic load, or oscilloscope to this header.
4.1.3
J3 – GND
J3 is the return connection of the LDO. A load can be connected between J3 and J1 (VLDO).
4.1.4
J4 – VINLDO
This header is the input supply for the LDO on the EVM VINLDO and is directly connected to VIN with R1.
An external power supply can be connected between J4 (VINLDO) and J6 (GND). Note that the resistors
R1 must be removed when supplying the LDO from an external power supply.
An external power supply can be connected between J4 (VINLDO) and J6 (GND). Note that the resistors
R1 must be removed when supplying the LDO from an external power supply.
4.1.5
J5 – S+/S–
J5 S+/S– is the sense connection for the input power supply of the LDO. Connect a voltmeter, sense
connection of a power supply, or oscilloscope to this header.
connection of a power supply, or oscilloscope to this header.
4.1.6
J6 – GND
J6 is the return connection of the input power supply for the LDO on the EVM. The input of the LDO is
directly connected to VIN with R1. Connect an input power supply of the LDO between J4 (VINLDO) and
J6.
directly connected to VIN with R1. Connect an input power supply of the LDO between J4 (VINLDO) and
J6.
4.1.7
J7 – VOUT DCDC2
This header is the positive output of VDCDC2 step-down converter. The output voltage of DCDC2 is fixed
to 1.8 V from the TPS657051 and TPS657052.
to 1.8 V from the TPS657051 and TPS657052.
VDCDC2 is capable of sourcing up to 400 mA. A load can be connected between J7 and J9 (GND).
4.1.8
J8 – S+/S–
J8 S+/S– are the sense connection for the output of DCDC2. Connect a voltmeter, sense connection of an
electronic load, or oscilloscope to this header.
electronic load, or oscilloscope to this header.
4.1.9
J9 – GND
J8 is the return connection of VDCDC2 output rail. A load can be connected between J9 and J7
(VDCDC2).
(VDCDC2).
4.1.10
J4 – VIN
This header is the input supply for the dc/dc converters. Connect a power supply between J12 (GND) and
J10.
J10.
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TPS657051/2EVM-522 Evaluation Module
SLVU366 – April 2010
Copyright © 2010, Texas Instruments Incorporated